MPC106ARX66TG datasheet, PDF - EEWORLD Datasheet

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MPC106ARX66TG: DescriptionPCI Bridge/Memory Controller; CategoryThe embedded processor and controller Microcontrollers and processors; File Size147KB，28 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MPC106ARX66TG Overview

PCI Bridge/Memory Controller

MPC106ARX66TG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
package instruction	BGA,
Reach Compliance Code	unknow
ECCN code	3A001.A.3
Address bus width	32
Bus compatibility	60X; POWERPC 601; POWERPC 603; POWERPC 604
maximum clock frequency	66 MHz
External data bus width	64
JESD-30 code	R-CBGA-B304
length	25 mm
Humidity sensitivity level	1
Number of terminals	304
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	3.16 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	21 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

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Order Number: MPC106EC/D

Rev. 5, 8/2001

Semiconductor Products Sector

Technical Data

MPC106 PCI Bridge/Memory Controller

Hardware Speciﬁcations

The Motorola MPC106 PCI bridge/memory controller provides a PowerPC™ microprocessor common

hardware reference platform (CHRP™) compliant bridge between the PowerPC microprocessor family

and the Peripheral Component Interconnect (PCI) bus. In this document, the term ‘106’ is used as an

abbreviation for the phrase ‘MPC106 PCI bridge/memory controller.’ This document contains pertinent

physical characteristics of the 106. For functional characteristics, refer to the

MPC106 PCI

Bridge/Memory Controller User’s Manual

This document contains the following topics:

Topic

Page

Section 1.1, “Overview”

Section 1.2, “Features”

Section 1.3, “General Parameters”

Section 1.4, “Electrical and Thermal Characteristics”

Section 1.5, “Pin Assignments”

Section 1.6, “Pinout Listings

Section 1.7, “Package Description”

Section 1.8, “System Design Information”

Section 1.9, “Document Revision History”

Section 1.10, “Ordering Information”

This document contains information on a new product under development by Motorola.

Motorola reserves the right to change or discontinue this product without notice.

Features

The 106 provides a PowerPC microprocessor CHRP-compliant bridge between the PowerPC

microprocessor family and the PCI bus. CHRP documentation provides a set of speciﬁcations that deﬁne a

uniﬁed personal computer architecture. PCI support allows the rapid design of systems using peripherals

already designed for PCI and the other standard interfaces available in the personal computer hardware

environment. The 106 integrates secondary cache control and a high-performance memory controller, uses

an advanced, 3.3-V CMOS process technology, and is fully compatible with TTL devices.

The 106 supports a programmable interface to a variety of PowerPC microprocessors operating at select

bus speeds. The 60x address bus is 32 bits wide and the data bus is 64 bits wide. The 60x processor

interface of the 106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers.

The address and data buses are decoupled to support pipelined transactions.

The 106 provides support for the following conﬁgurations of 60x processors and L2 cache:

•

Up to four 60x processors with no L2 cache

A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal L2 cache

controller of the 106

Up to four 60x processors plus an externally controlled L2 cache (such as the Motorola MPC2605

integrated secondary cache)

The memory interface controls processor and PCI interactions to main memory and is capable of

supporting a variety of conﬁgurations using DRAM, EDO, SDRAM, ROM, or Flash ROM.

The PCI interface of the 106 complies with the

PCI Local Bus Speciﬁcation,

Revision 2.1, and follows the

guidelines in the

PCI System Design Guide,

Revision 1.0, for host bridge architecture. The PCI interface

connects the processor and memory buses to the PCI bus, to which I/O components are connected. The PCI

bus uses a 32-bit multiplexed address/data bus, plus various control and error signals.

The PCI interface of the 106 functions as both a master and target device. As a master, the 106 supports

read and write operations to the PCI memory space, the PCI I/O space, and the PCI conﬁguration space.

The 106 also supports PCI special-cycle and interrupt-acknowledge commands. As a target, the 106

supports read and write operations to system memory.

The 106 provides hardware support for four levels of power reduction: doze, nap, sleep, and suspend. The

design of the MPC106 is fully static, allowing internal logic states to be preserved during all power-saving

modes.

1.2 Features

This section summarizes the major features of the 106, as follows:

•

60x processor interface

— Supports up to four 60x processors

— Supports various operating frequencies and bus divider ratios

— 32-bit address bus, 64-bit data bus

— Supports full memory coherency

— Supports optional 60x local bus slave

— Decoupled address and data buses for pipelining of 60x accesses

— Store gathering on 60x-to-PCI writes

MPC106 PCI Bridge/Memory Controller Hardware Speciﬁcations

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