BU-65142 and BUS-65142 SERIES*
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
DESCRIPTION
The BUS-65142 Series is a com-
plete dual redundant MIL-STD-
1553 Remote Terminal Unit (RTU).
The device is based upon two DDC
custom ICs, which includes two
monolithic bi-polar low power trans-
ceivers and one CMOS protocol
containing data buffers and timing
control logic. It supports all 13 mode
codes for dual redundant operation,
any combination of which can be ille-
galized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BUS-65142 Series spe-
cial features. A 14-bit built-in-test
word register stores RTU information,
and sends it to the Bus Controller in
response to the Mode Command
Transmit Bit Word. The BUS-65142
Series performs continuous on-line
wraparound self-test, and provides
four error flags to the host CPU.
Inputs are provided for host CPU con-
trol of 6 bits of the RTU Status Word.
Its
small
hermetic
package,
-55°C to +125°C operating tempera-
ture range, and complete RTU opera-
tion make the BUS-65142 ideal for
most MIL-STD-1553 applications
requiring hardware or microprocessor
subsystems.
FEATURES
•
Complete Integrated Remote
Terminal Including:
–Dual Low-Power Transceivers
–Complete RT Protocol
•
Multiple Ordering Options;
+5V (Only), +5V/-15V, and +5V/-12V
•
Direct Interface to Systems With
No Processor
•
Radiation Tolerant Version
Available
•
Space Qualified Version Available
•
High Reliability Screening Available
*
(Note:
BUS-65142 is NOT recommended for new design, use BU-61703/05 Simple System RT for new designs.
BU-65142 is NOT recommended for new design, consult factory or local representative for more information)
DATA
BUS A
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
BUFFER
DB0-DB15
BUF ENA
DTREQ
DTGRT
DTACK
DTSTR
R/W
WATCHDOG
TIMEOUT
TRANSFER
CONTROLS
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
CURRENT
WORD
COUNTER
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
M
U
X
A0-A4
A5-A10
DAT/CMD
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
NBGT
INCMD
BITEN
STATEN
GBR
COMMAND
LATCH
RT ADDRESS
+
PARITY
STATUS
REGISTER
16 MHz CLOCK
ERROR FLAGS
TIMING FLAGS
DDC CUSTOM CHIP
FIGURE 1. BUS-65142 SERIES BLOCK DIAGRAM
©
1988, 1999 Data Device Corporation
TABLE 1. BU-65142 and BUS-65142/44 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +5V
Transceiver +5V
-15V (BUS-65142, BU-65142X1)
-12V (BUS-65143, BU-65142X1/2)
Receiver Differential Voltage
Logic
Voltage Input Range for +5V
RECEIVER
Differential Input Impedance
(DC to 1 MHz)
Differential Input Voltage
Input Threshold Level
(Direct Coupled)
CMRR (DC to 2 MHz)
CMV (DC to 2 MHz)
TRANSMITTER
Differential Output Voltage
!
Direct Coupled Across 35
Ω,
Measured on Bus
!
Transformer Coupled Across 70
Ω,
Measured on Stub
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, (Transformer
Coupled Across 70 ohms)
Rise/Fall Time
LOGIC
V
IH
V
IL
I
IH
(V
IH
=2.7V)
!
BRO ENA,
ADDRE-ADDRA(RTAD4-RTAD0),
ADDRP (connect to 30kΩ pull-up )
!
(V
IH
=2.7V) DB15 - DB0
(connect to a 45kΩ pull-up )
!
(V
IH
≥2.4V)
All Other Inputs
I
IL
(VIL=0.4V)
!
BRO ENA,
ADDRE-ADDRA(RTAD4-RTAD0),
ADDRP (connect to 30kΩ pull-up )
!
(V
IL
=0.4V) DB15 - DB0
(connect to a 45kΩ pull-up )
!
(V
IL
=≥0.7V) All Other Inputs
V
OH
!
(I
OH
=-0.4mA)
A9-A5(SA4-SA0), RTADERR,
HSFAIL, DAT/CMD, RTFAIL, BITEN,
NBGT, GBR, ME, STATEN
V
OH
!
(I
OH
=-0.4mA) All Other Inputs
V
OH
!
(I
OH
=-0.4mA) DB15 - DB0
(connected to a 45kΩ pull-up )
MIN
TYP
MAX
UNITS
TABLE 1. BU-65142 and BUS-65142/44 SPECIFICATIONS (continued)
PARAMETER
LOGIC (continued)
V
OL
!
(I
OL
=-2mA)
MIN
TYP
MAX
UNITS
-0.5
-0.5
-18.0
-18.0
7.0
7.0
0.3
0.3
40.0
7.0
V
V
V
V
Vp-p
V
kohm
0.4
V
A9-A5(SA4-SA0), RTADERR,
HSFAIL, DAT/CMD, RTFAIL,
BITEN, NBGT, GBR, ME, STATEN
V
OL
!
(I
OL
=2 mA) All Other Inputs
V
OL
!
(I
OL
= 2mA) DB15 - DB0
(connected to a 45kΩ pull-up )
C
IN
(f = 1 MHz)
C
0
(f = 1 MHz)
C
I0
(f = 1 MHz)
LOGIC (CONT) (BU-65142 ONLY)
V
OH
!
(I
OH
= 6ma), VDD = 4.5V
BU-65142 ONLY
V
OL
!
(I
OL
= 6mA), VDD = 4.5V
BU-65142 ONLY
-0.5
4.0
0.4
V
0.4
V
40
0.70
40
±10
1.20
Vp-p
Vp-p
dB
V
50
10
50
pF
pF
pF
6
18
7
20
9
27
10
Vp-p
Vp-p
4.0
V
0.5
V
-250
100
2.4
150
mVp-p,
diff
+250 mVp-p,
diff
300
nsec
V
V
mA
POWER SUPPLY REQUIREMENTS
+5V Logic Power (BU-65142X1/2,
BUS-65142/43/44/45)
Current Drain
+5V (BU-65142X3)
Current Drain
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
-15V (BU-65142X1, BUS-
65142/44)
Current Drain
• Idle
• 50% Transmitter Duty Cycle
• 25% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
-12V (BU-65142X2, BUS-65143/45)
Current Drain
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
4.5
5.5
115
V
mA
V
mA
mA
mA
mA
V
0.7
0.04
0.2
4.75
5.0
5.25
125
230
335
545
0.04
0.2
±20
mA
µA
-15.75
-14.25
0.4
mA
0.4
±20
mA
µA
60
108
160
255
-12.6
-11.4
60
120
185
305
mA
mA
mA
mA
V
mA
mA
mA
mA
2.4
V
2.4
V
2.4
V
Data Device Corporation
www.ddc-web.com
2
BU-65142 and BUS-65142 SERIES
U-05/02-0
TABLE 1. BU-65142 and BUS-65142/44 SPECIFICATIONS (continued)
PARAMETER
POWER DISSIPATION (See Note)
Total Hybrid
!
BU-65142X1/BUS-65142/44
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65142X2/BUS-65143/45
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65142X3
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
!
BU-65142X1/BUS-65142/44
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65142X2/BUS-65143/45
Note (for TABLE 1):
Power dissipation specifications assume a transformer coupled
configuration, with external dissipation (while transmitting) of
0.14 watts for the active isolation transformer, 0.08 watts for the
active coupling transformer, 0.45 watts for each of the two bus
isolation resistors, and 0.15 watts for each of the two bus termi-
nation resistors.
MIN
TYP
MAX
UNITS
1.475
1.856
2.238
3.000
1.295
1.680
2.065
2.895
0.687
0.92
1.15
1.60
W
W
W
W
W
W
W
W
W
W
W
W
TABLE 2. BU-65142 SERIES RADIATION SPECIFICATIONS
PART
NUMBER
TOTAL
DOSE
SINGLE EVENT
UPSET
SINGLE EVENT
LATCHUP
BU-65142
X1/X2
300K
Rad
5.3 x 10
-6
errors/device-day,
(LET Threshold of
59 MeV/mg/cm
2
)
5.3 x 10
-6
errors/device-day,
(LET Threshold of
59 MeV/mg/cm
2
)
Immune
0.680
1.010
1.350
2.030
0.290
0.540
0.790
1.290
W
W
W
W
W
W
W
W
BU-65142
X3
175K
Rad
Immune
•
•
•
•
•
•
•
•
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
!
BU-65142X3
0.28
0.51
0.75
1.22
W
W
W
W
THERMAL
• Thermal Resistance, Junction-to-
Case, Hottest Die (θJC)
• Operating Junction Temperature
• Operating Junction Temperature
(BU-65142 ONLY)
• Storage Temperature
• Lead Temperature
(soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Size
78-pin Kovar (BUS-65142/43)
20
-55
-55
-65
150
125
150
+300
°C/W
°C
°C
°C
°C
1.87 x 2.10 x 0.25
(47.5 x 53.3 x 6.4)
1.61 x 2.20 x 0.181
(40.8 x 55.8 x 4.6)
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
1.7
(48.2)
in
(mm)
in
(mm)
in
(mm)
in
(mm)
oz
(g)
82-pin Kovar Flat Pack
(BUS-65144/45)
78-pin Ceramic QIP (BU-65142D)
78-pin Ceramic Flat Pack
(BU-65142F)
Weight
Data Device Corporation
www.ddc-web.com
3
BU-65142 and BUS-65142 SERIES
U-05/02-0
INTRODUCTION
The BUS-65142 is a complete dual redundant Remote Terminal
Unit (RTU). It is fully compliant with MIL-STD-1553B and sup-
ports all message formats. As shown in FIGURE 1, it includes
2 transceivers and a custom chip containing 2 encoders, 2 bit
processors, an RTU protocol sequencer and control logic, output
latches, and buffers. With the addition of 2 data bus transform-
ers, the BUS-65142 is ready for connection to a MIL-STD-1553
data bus.
Data is transferred to and from the subsystem host CPU over a
16-bit parallel highway, which is isolated by a set of bi-direction-
al buffers. All transfers are made with a DMA type handshake
sequence of request, grant and acknowledge. Read/write and
data strobes are provided to simplify interfacing to external
RAM. Also simplifying the RAM interface is the availability of a
latched command word and an auto-incrementing word counter.
These signals may be used as an address to map the data
directly to and from RAM.
The BUS-65142 allows the subsystem host CPU to control 6 of
the bits in the RTU status word. Of particular interest is the
Illegal Command input which may be used to set the message
error bit and illegalize any command word. The BUS-65142 pro-
vides four error flags to the subsystem host CPU for evaluating
its condition. In addition a continuous on-line self-test is per-
formed by the BUS-65142 on every transmission. The last
Transmitted Word of every message is wrapped around the
decoder and compared with the Actual Word. Any discrepancy
is flagged as an error.
RT to RT address error
T/R bit error.
The RTFAIL (Remote Terminal Failure) line goes LOW
whenever the results of a continuous wraparound self-test
shows a discrepancy, or a transmitter watchdog timeout
has occurred.
The HSFAIL (Handshake Failure) line goes LOW whenev-
er the system does not issue a DTGRT in response to a
DTREQ before timing-out.
The RTADR ERR (RT Address Error) line goes LOW when-
ever the sum of the 5 address lines and parity lines show a
parity error (the terminal will not respond to commands
while this error condition exists).
STATUS REGISTER
Six inputs to the BUS-65142 allow the subsystem host CPU to
control bits in the RTU status word. The Illegal Command input
may be used to set the Message Error bit in the Status Word and
suppress the transmission of data to the bus controller. This line
allows illegalization of any combination of commands. The
latched Command Word may be connected to the address pins
of an optional external PROM, which would drive the illegal
Command line LOW when it identifies a command programmed
as illegal.
STATUS REGISTER BIT ASSIGNMENTS
The SRQ (Subsystem Request) line is used to set the
Status Word service request bit.
The ADBC (Accept Dynamic Bus Control) line is used to
set the Status Word bus control bit.
The RTFLAG (RT Flag Line) is used to set the Status Word
terminal flag bit.
The BUSY (Busy) line is used to set the Status Word busy
bit, and inhibit subsystem requests for data.
The SSFLAG (SubSystem Flag) line is used to set the
Status Word subsystem (fault) flag.
TIMING
Interfacing the subsystem host CPU to the BUS-65142 is simple
and compatible with most microprocessors. FIGURES 4 and 5
illustrate typical MIL-STD-1553 messages for Transmit data and
Receive data. FIGURES 6 and 7 illustrate RT to RT transfers. In
each case NBGT identifies the start of the message, and
INCMD identifies that a command is being processed. The hand-
shake sequence DTREQ , DTGRT, and DTACK is used to trans-
fer each word over the parallel data highway. DTSRB and
RD/WR are used to control transfers to RAM memory. GBR
identifies a “good block received”, when a received message has
passed all validation checks and has the correct word count.
BUFENA (Buffer Enable) must be applied to enable the internal
tri-state buffers.
BUILT-IN-TEST
The BUS-65142 contains a 14-bit Built-In-Test (BIT) word regis-
ter which stores information about the condition of the RTU.
When a mode code is received to transmit the BIT word, the con-
tents of the BIT register is transmitted over the 1553 bus.
FIGURE 2 shows the fault assigned to each bit in the BIT word.
Conditions monitored are; transmitter timeouts, loop test failures,
transmitter shutdown, subsystem handshake failure, and the
results of individual message validations.
ERROR FLAGS
Four error flags are output to the subsystem to provide informa-
tion on the condition of the BUS-65142.
The ME (Message Error) line goes LOW if any of the fol-
lowing error conditions exist:
format error
word count error
invalid word
sync error
Data Device Corporation
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4
BU-65142 and BUS-65142 SERIES
U-05/02-0
DATA BUS
Z
0 (70 to 85
Ω)
DIRECT COUPLED (SHORT STUB)
1.4:1
55
Ω
+5V
-15V
BUS-65142
BUS-65144
BU-65142D1
BU-65142F1
1 FT MAX
55
Ω
39 VPP
ISOLATION
TRANSFORMER
28 VPP
OR
TRANSFORMER COUPLED (LONG STUB)
2:1
1:1.4
20 FT MAX
8
4
1
3
0.75 Z
0
28 VPP
0.75 Z
0
39 VPP
ISOLATION
TRANSFORMER
20 VPP
COUPLING
TRANSFORMER
DIRECT COUPLED (SHORT STUB)
1:0.83
55
Ω
+5V
-12V
BUS-65143
BUS-65145
BU-65142D2
BU-65142F2
1 FT MAX
55
Ω
33 VPP
ISOLATION
TRANSFORMER
28 VPP
OR
TRANSFORMER COUPLED (LONG STUB)
1:0.6
1:1.4
20 FT MAX
8
4
1
3
0.75 Z
0
28 VPP
0.75 Z
0
33 VPP
ISOLATION
TRANSFORMER
20 VPP
COUPLING
TRANSFORMER
DIRECT COUPLED (SHORT STUB)
1:2.5
55
Ω
1 FT MAX
+5V
BU-65142D3
BU-65142F3
55
Ω
11.6 VPP
ISOLATION
TRANSFORMER
28 VPP
OR
TRANSFORMER COUPLED (LONG STUB)
1:1.79
1:1.4
20 FT MAX
8
4
1
3
0.75 Z
0
28 VPP
0.75 Z
0
11.6VPP
ISOLATION
TRANSFORMER
20 VPP
COUPLING
TRANSFORMER
FIGURE 2. INTERFACE TO 1553 BUS
Data Device Corporation
www.ddc-web.com
5
Z
0
(70 to 85
Ω)
BU-65142 and BUS-65142 SERIES
U-05/02-0
FPGA/CPLD
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