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HY27SS08121A-TMP

Description
Flash, 64MX8, 40ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48
Categorystorage    storage   
File Size414KB,49 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance  
Download Datasheet Parametric View All

HY27SS08121A-TMP Overview

Flash, 64MX8, 40ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48

HY27SS08121A-TMP Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeTSOP1
package instruction12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48
Contacts48
Reach Compliance Codecompliant
ECCN code3A991.B.1.A
Is SamacsysN
Maximum access time40 ns
JESD-30 codeR-PDSO-G48
JESD-609 codee6
length18.4 mm
memory density536870912 bit
Memory IC TypeFLASH
memory width8
Number of functions1
Number of terminals48
word count67108864 words
character code64000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
organize64MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Programming voltage1.8 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)1.95 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTIN BISMUTH
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
typeNAND TYPE
width12 mm
Base Number Matches1
HY27US(08/16)121A Series
HY27SS(08/16)121A Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
History
Draft Date
Sep. 2004
Remark
Preliminary
0.1
1) Correct part number ( change mode)
- 2A -> 1A (sequential row read : disable -> enable)
2) Correct Table.5 & Table 12
- Correct Command Set
- correct AC timing characteristics (tWP : 40 -> 25ns, tWH : 20 ->15ns)
3) Correct Summary description & page.7
- The cache feature is deleted in summary description.
Oct. 22. 2004
- Note.3 is deleted. (page.7)
4) Add System interface using CE don’t care (page. 38)
5) Change TSOP1, WSOP1,FBGA package dimension & figures.
- Change TSOP1, WSOP1, FBGA package mechanical data
- Change TSOP1, WSOP package figures
6) Correct TSOP1, WSOP1 Pin configuration
- 38th NC pin has been changed Lockpre (figure 2,3)
7) Add Bad block Management
1) LOCKPRE is changed to PRE
- Texts, Table and figures are changed.
2) Change Command set
- Read A,B are changed to Read1.
- Read C is changed to Read2.
3) Change AC, DC characterics
Preliminary
0.2
- tRB, tCRY, tCEH and tOH are added.
4) Correct Program time (max)
- before : 700us
- after
: 500us
5) Edit figures
- Address names are changed.
6) Change FBGA Package Dimension
- FD1 : 1.70(before) -> 0.90(after)
Mar. 08. 2005 Preliminary
Rev 1.3 / Jun. 2006
1
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