EPF10K50SQI240-2X datasheet, PDF

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EPF10K50SQI240-2X: DescriptionLoadable PLD, 9.5ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, PLASTIC, QFP-240; CategoryProgrammable logic devices Programmable logic; File Size2MB，108 Pages; ManufacturerAltera (Intel)

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EPF10K50SQI240-2X Overview

Loadable PLD, 9.5ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, PLASTIC, QFP-240

EPF10K50SQI240-2X Parametric

Parameter Name	Attribute value
Maker	Altera (Intel)
Parts packaging code	QFP
package instruction	FQFP,
Contacts	240
Reach Compliance Code	unknown
Is Samacsys	N
JESD-30 code	S-PQFP-G240
JESD-609 code	e3
length	32 mm
Number of I/O lines	189
Number of terminals	240
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	189 I/O
Output function	MIXED
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Programmable logic type	LOADABLE PLD
propagation delay	9.5 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	32 mm
Base Number Matches	1

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FLEX 10KE

Embedded Programmable

Logic Devices

Data Sheet

January 2001, ver. 2.2

Features...

Embedded programmable logic devices (PLDs), providing

system-on-a-programmable-chip (SOPC) integration in a single

device

–

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

–

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

–

Logic array for general logic functions

High density

–

30,000 to 200,000 typical gates (see Tables 1 and 2)

–

Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be

used without reducing logic capacity

System-level features

–

MultiVolt

I/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

–

Low power consumption

–

Bidirectional I/O performance (t

and

) up to 250 MHz

–

Fully compliant with the PCI Special Interest Group (PCI SIG)

PCI Local Bus Specification, Revision 2.2

for 3.3-V operation at

33 MHz or 66 MHz

–

-1 speed grade devices are compliant with

PCI Local Bus

Specification, Revision 2.2,

for 5.0-V operation

–

Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming additional device logic

For information on 5.0-V FLEX

10K or 3.3-V FLEX 10KA devices, see the

FLEX 10K Embedded Programmable Logic Family Data Sheet.

Table 1. FLEX 10KE Device Features

Feature

Typical gates

(1)

Maximum system gates

Logic elements (LEs)

EABs

Total RAM bits

Maximum user I/O pins

Altera Corporation

A-DS-F10KE-02.2

EPF10K30E

30,000

119,000

1,728

24,576

220

EPF10K50E

EPF10K50S

50,000

199,000

2,880

40,960

254

EPF10K100B

100,000

158,000

4,992

24,576

191

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