EP20K600EFC1020-2X datasheet, PDF

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EP20K600EFC1020-2X: DescriptionLoadable PLD, 0.4ns, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FINE LINE, BGA-1020; CategoryProgrammable logic devices Programmable logic; File Size628KB，117 Pages; ManufacturerAltera (Intel)

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EP20K600EFC1020-2X Overview

Loadable PLD, 0.4ns, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FINE LINE, BGA-1020

EP20K600EFC1020-2X Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	HBGA, BGA1020,32X32,40
Contacts	1020
Reach Compliance Code	compliant
Is Samacsys	N
maximum clock frequency	160 MHz
JESD-30 code	S-PBGA-B1020
JESD-609 code	e0
length	33 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	588
Number of entries	588
Number of logical units	24320
Output times	588
Number of terminals	1020
Maximum operating temperature	85 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 588 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	HBGA
Encapsulate equivalent code	BGA1020,32X32,40
Package shape	SQUARE
Package form	GRID ARRAY, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	220
power supply	1.8,2.5,3.3 V
Programmable logic type	LOADABLE PLD
propagation delay	0.4 ns
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	33 mm
Base Number Matches	1

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APEX 20K

Programmable Logic

Device Family

March 2004, ver. 5.1

Data Sheet

Features

■

Industry’s first programmable logic device (PLD) incorporating

system-on-a-programmable-chip (SOPC) integration

–

MultiCore

architecture integrating look-up table (LUT) logic,

product-term logic, and embedded memory

–

LUT logic used for register-intensive functions

–

Embedded system block (ESB) used to implement memory

functions, including first-in first-out (FIFO) buffers, dual-port

RAM, and content-addressable memory (CAM)

–

ESB implementation of product-term logic used for

combinatorial-intensive functions

High density

–

30,000 to 1.5 million typical gates (see

Tables 1

and

–

Up to 51,840 logic elements (LEs)

–

Up to 442,368 RAM bits that can be used without reducing

available logic

–

Up to 3,456 product-term-based macrocells

Note (1)

EP20K100

263,000

Table 1. APEX 20K Device Features

Feature

Maximum

system

gates

Typical

gates

LEs

ESBs

Maximum

RAM bits

Maximum

macrocells

Maximum

user I/O

pins

EP20K30E

113,000

EP20K60E

162,000

EP20K100E

263,000

EP20K160E

404,000

EP20K200

526,000

EP20K200E

526,000

30,000

1,200

24,576

192

128

60,000

2,560

32,768

256

196

100,000

4,160

53,248

416

252

100,000

4,160

53,248

416

246

160,000

6,400

81,920

640

316

200,000

8,320

106,496

832

382

200,000

8,320

106,496

832

376

Altera Corporation

DS-APEX20K-5.1

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