3. Switching characteristics are independent of operating junction temperature.
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2
MMDF1N05E, MVDF1N05E
TYPICAL ELECTRICAL CHARACTERISTICS
10
10 V
I D , DRAIN CURRENT (AMPS)
8
4.5 V
6
4V
4
V
GS
= 3.5 V
10
5V
I D , DRAIN CURRENT (AMPS)
8
V
DS
≥
10 V
- 55°C
25°C
100°C
6V
8V
T
J
= 25°C
6
4
25°C
2
0
2
100°C
- 55°C
3
4
5
6
7
8
0
4
6
8
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
2
10
0
0
1
2
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE (OHMS)
RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE
(NORMALIZED)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
- 50
- 25
Figure 2. Transfer Characteristics
0.5
V
GS
= 10 V
0.4
V
GS
= 10 V
I
D
= 1.5 A
0.3
0.2
100°C
25°C
0.1
- 55°C
0
0
2
4
I
D
, DRAIN CURRENT (AMPS)
6
8
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 3. On−Resistance versus Drain Current
V GS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 4. On−Resistance Variation with Temperature
0.5
I
D
= 1.5 A
0.4
1.2
V
DS
= V
GS
I
D
= 1 mA
1.1
0.3
1
0.2
0.9
0.1
0.8
0
2
3
4
5
6
7
8
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
9
10
0.7
- 50
- 25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. On Resistance versus
Gate−To−Source Voltage
Figure 6. Gate Threshold Voltage Variation
with Temperature
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3
MMDF1N05E, MVDF1N05E
1200
1000
C, CAPACITANCE (pF)
800
V
DS
= 0
600
400
200
0
C
iss
C
oss
C
rss
25
15
5
5
10
15
20
10
0
20
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V
GS
= 0
V
GS
C
iss
C
rss
T
J
= 25°C
0
V
DS
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
12
10
8
6
4
2
0
V
DS
= 25 V
I
D
= 1.2 A
0
2
4
6
8
10
12
Q
g
, TOTAL GATE CHARGE (nC)
14
16
Figure 7. Capacitance Variation
Figure 8. Gate Charge versus
Gate−To−Source Voltage
100
I D , DRAIN CURRENT (AMPS)
V
GS
= 20 V
SINGLE PULSE
T
C
= 25°C
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
SAFE OPERATING AREA INFORMATION
Forward Biased Safe Operating Area
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. ON
Semiconductor Application Note, AN569, “Transient
Thermal Resistance
−
General Data and Its Use” provides
detailed instructions.
10
10 ms
1
dc
100
ms
10
ms
0.1
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
100
0.01
0.1
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
10
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
Normalized to
qja
at 10s.
Chip
0.0175
W
0.0710
W
0.2706
W
0.5776
W
0.7086
W
0.01
SINGLE PULSE
0.001
1.0E-05
1.0E-04
1.0E-03
1.0E-02
0.0154 F
0.0854 F
0.3074 F
1.7891 F
107.55 F
Ambient
1.0E+03
1.0E-01
t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
Figure 10. Thermal Response
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4
MMDF1N05E, MVDF1N05E
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AK
−X−
A
8
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
_
8
_
0.25
0.50
5.80
6.20
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
_
8
_
0.010
0.020
0.228
0.244
B
1
S
4
0.25 (0.010)
M
Y
M
−Y−
G
K
C
−Z−
H
D
0.25 (0.010)
M
SEATING
PLANE
N
X 45
_
0.10 (0.004)
M
J
Z Y
S
X
S
SOLDERING FOOTPRINT*
1.52
0.060
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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