ispGDX2™ Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) #09-10 has been issued to discontinue select
devices in this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
LX64V
Ordering Part Number
LX64V-3F100C
LX64V-3FN100C
LX64V-5F100C
LX64V-5FN100C
LX64B-3F100C
LX64B-3FN100C
LX64B-5F100C
LX64B-5FN100C
LX64C-3F100C
LX64C-3FN100C
LX64C-5F100C
LX64C-5FN100C
LX128V-32F208C
LX128V-32FN208C
LX128V-5F208C
LX128V-5FN208C
LX128B-32F208C
LX128B-32FN208C
LX128B-5F208C
LX128B-5FN208C
LX128C-32F208C
LX128C-32FN208C
LX128C-5F208C
LX128C-5FN208C
LX256V-35F484C
LX256V-35FN484C
LX256V-5F484C
LX256V-5FN484C
LX256B-35F484C
LX256B-35FN484C
LX256B-5F484C
LX256B-5FN484C
Product Status
Active / Orderable
Reference PCN
LC64B
Discontinued
PCN#09-10
LX64C
Discontinued
PCN#09-10
LX128V
Active / Orderable
LX128B
Discontinued
PCN#09-10
LX128C
Discontinued
PCN#09-10
LX256V
Active / Orderable
LX256B
Discontinued
PCN#09-10
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
ispGDX2
™
Family
September 2005
Features
Includes
High-
,
Performance
Low-Cost
“E-Series”
High Performance Interfacing and Switching
Data Sheet
■
Two Options Available
• High-performance sysHSI (standard part number)
• Low-cost, no sysHSI (“E-Series”)
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
• High bandwidth
– Up to 12.8 Gbps (SERDES)
– Up to 38 Gbps (without SERDES)
• Up to 16 (15x10) FIFOs for data buffering
• High speed performance
– f
MAX
= 360MHz
– t
PD
= 3.0ns
– t
CO
= 2.9ns
– t
S
= 2.0ns
• Built-in programmable control logic capability
• I/O intensive: 64 to 256 I/Os
• Expanded MUX capability up to 188:1 MUX
•
•
•
•
Frequency synthesis and skew management
Clock multiply and divide capability
Clock shifting up to +/-2.35ns in 335ps steps
Up to four PLLs
•
•
•
•
•
■
High Performance Bus Switching
■
sysHSI Blocks Provide up to 16 High-speed
Channels
Serializer/de-serializer (SERDES) included
Clock Data Recovery (CDR) built in
800 Mbps per channel
LVDS differential support
10B/12B support
– Encoding / decoding
– Bit alignment
– Symbol alignment
• 8B/10B support
– Bit alignment
– Symbol alignment
• Source Synchronous support
■
sysCLOCK™ PLL
■
Flexible Programming and Testing
■
sysIO™ Interfacing
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
standard board interfaces
• SSTL 2/3 Class I and II support
• HSTL Class I, III and IV support
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
I/Os
64
4
• IEEE 1532 compliant In-System Programmabil-
ity (ISP™)
• Boundary scan test through IEEE 1149.1
interface
• 3.3V, 2.5V or 1.8V power supplies
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
ispGDX2-64/E
ispGDX2-128/E
128
8
ispGDX2-256/E
256
16
GDX Blocks
t
PD
t
S
3.0ns
2.9ns
3.2ns
3.1ns
3.5ns
3.2ns
2.0ns
2.0ns
2.0ns
t
CO
f
MAX
(Toggle)
360MHz
11Gbps
4
32
2
330MHz
21Gbps
8
64
2
300MHz
38Gbps
16
128
4
Max Bandwidth
SERDES
1, 2
3.2Gbps
6.4Gbps
12.8Gbps
Without SERDES
3
sysHSI Channels
2
LVDS/Bus LVDS (Pairs)
PLLs
Package
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. f
MAX
(Toggle) * maximum I/Os divided by 2.
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13
Lattice Semiconductor
Figure 1. ispGDX2 Block Diagram (256-I/O Device)
sysIO Bank
sysHSI
Block
ispGDX2 Family Data Sheet
sysIO Bank
SERDES
FIFO
SERDES
FIFO
sysHSI
Block
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
FIFO
FIFO
sysHSI
Block
sysHSI
Block
sysCLOCK
PLL
SERDES
SERDES
sysCLOCK
PLL
GDX Block
GDX Block
GDX Block
GDX Block
GDX Block
GDX Block
SERDES
SERDES
SERDES
SERDES
SERDES
FIFO
FIFO
sysIO Bank
Introduction
The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for
high speed bus switching and interface applications.
The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the
sysHSI Block.
This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high
performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through
a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.
The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,
the family supports bandwidth up to 38Gbps.
Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple
clocks and manage clock skews in their systems.
sysIO Bank
sysIO Bank
GDX Block
GDX Block
SERDES
FIFO
FIFO
FIFO
FIFO
Global Routing Pool
(GRP)
GDX Block
GDX Block
GDX Block
GDX Block
SERDES
FIFO
FIFO
sysIO Bank
SERDES
sysHSI
Block
sysCLOCK
PLL
sysHSI
Block
GDX Block
GDX Block
GDX Block
GDX Block
FIFO
FIFO
FIFO
FIFO
sysHSI
Block
SERDES
SERDES
SERDES
SERDES
sysHSI
Block
sysCLOCK
PLL
sysIO Bank
sysIO Bank
ISP & Boundary Scan
Test Port
2
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
