PRELIMINARY
DS1746/DS1746P
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identical to the
static RAM. These registers are resident in the
eight top RAM locations.
Century byte register; ie., Y2K compliant
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100
Battery voltage level indicator flag
Power-fail write protection allows for ±10%
V
CC
power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
DIP Module only
- Standard JEDEC Byte-wide 128k x 8
static RAM pinout
PowerCap Module Board only
- Surface mountable package for direct
connection to PowerCap containing
battery and crystal
- Replaceable battery (PowerCap)
- Power-On Reset Output
- Pin for pin compatible with other densities
of DS174XP Timekeeping RAM
PIN ASSIGNMENT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-PIN ENCAPSULATED
PACKAGE
NC
A15
A16
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
X1
GND V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-PIN POWERCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
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021800
DS1746/DS1746P
PIN DESCRIPTION
A0–A16
CE
OE
WE
V
CC
GND
DQ0–DQ7
NC
RST
X1, X2
V
BAT
–
–
–
–
–
–
–
–
–
Address Input
Chip Enable
Output Enable
Write Enable
Power Supply Input
Ground
Data Input/Output
No Connection
Power–on Reset Output(Power–
Cap Module board only)
– Crystal Connection
– Battery Connection
ORDERING INFORMATION
DS1746P–XXX (5 Volt)
-70 70 ns access
-100 100 ns access
blank 32-pin DIP Module
P
34-pin PowerCap Module board*
DS1746WP-XXX (3.3 Volt)
-120 120 ns access
-150 150 ns access
blank 32-pin DIP Module
P
34-pin PowerCap Module
board*
*DS9034PCX (PowerCap) Required:
(must be ordered separately)
DESCRIPTION
The DS1746 is a full function, year 2000 compliant (Y2KC), real-time clock/calendar (RTC) and 128k x
8 non-volatile static RAM. User access to all registers within the DS1746 is accomplished with a
bytewide interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside
in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year
are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data
that can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1746 also contains its
own power-fail circuitry which deselects the device when the V
CC
supply is in an out of tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low V
CC
as errant access and update cycles are avoided.
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DS1746/DS1746P
DS1746 BLOCK DIAGRAM
Figure 1
PACKAGES
The DS1746 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1746P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCK
While the double buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1746 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table 2. As
long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1746 registers are updated simultaneously after the
internal clock register updating process has been re-enabled. Updating is within a second after the read bit
is written to zero.
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DS1746/DS1746P
DS1746 TRUTH TABLE
Table 1
V
CC
V
CC
>V
PF
V
SO
<V
CC
<V
PF
V
CC
<V
SO
CE
V
IH
V
IL
V
IL
V
IL
X
X
OE
X
X
V
IL
V
IH
X
X
WE
X
V
IL
V
IH
V
IH
X
X
MODE
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1746 registers. The user can then load them with the correct day, date and
time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual
clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1746 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The clock is
calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements.
The DS1746 does not require additional calibration and temperature deviations will have a negligible
effect in most applications. For this reason, methods of field clock calibration are not available and not
necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1746P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.
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DS1746/DS1746P
DS1746 REGISTER MAP
Table 2
ADDRESS
DATA
B
7
B
6
X
X
FT
X
B
5
B
4
B
3
B
2
B
1
10 YEAR
YEAR
X
10 MO
MONTH
10 DATE
DATE
X
X
X
DAY
10 HOUR
HOUR
10 MINUTES
MINUTES
10 SECONDS
SECONDS
10 CENTURY
CENTURY
R = READ BIT
X = SEE NOTE BELOW
B
0
FUNCTION/RANGE
1FFFF
1FFFE
X
1FFFD
X
1FFFC
BF
1FFFB
X
1FFFA
X
1FFF9
OSC
1FFF8
W
OSC = STOP BIT
W = WRITE BIT
YEAR
00-99
MONTH
01-12
DATE
01-31
DAY
01-07
HOUR
00-23
MINUTES
00-59
SECONDS
00-59
CENTURY
00-39
FT = FREQUENCY TEST
BF = BATTERY FLAG
R
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING
DATA FROM RAM OR CLOCK
The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
AA
after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip enable access (t
CEA
) or at output enable
access time (t
OEA
). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs
are activated before t
AA
, the data lines are driven to an intermediate state until t
AA
. If the address inputs
are changed while CE and OE remain valid, output data will remain valid for output data hold time (t
OH
)
but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs t
WEZ
after WE goes active.
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