DSPD56367AG150 datasheet, PDF - EEWORLD Datasheet

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DSPD56367AG150: Description24-BIT, 150 MHz, OTHER DSP, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，531 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Environmental Compliance

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DSPD56367AG150 Overview

24-BIT, 150 MHz, OTHER DSP, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144

DSPD56367AG150 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Rochester Electronics
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	144
Reach Compliance Code	unknown
Is Samacsys	N
Address bus width	18
barrel shifter	YES
boundary scan	YES
maximum clock frequency	150 MHz
External data bus width	24
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQFP-G144
JESD-609 code	e3
length	20 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	144
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	COMMERCIAL
Maximum seat height	1.6 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	20 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1

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TABLE OF CONTENTS

Paragraph

Number

Page

Number

CHAPTER 1

DSP56367 OVERVIEW

1.1

1.2

1.3

1.4

1.4.1

1.4.1.1

1.4.1.2

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.4.9

1.5

1.5.1

1.5.2

1.5.3

1.5.4

1.5.5

1.5.6

1.5.7

Introduction ......................................................................................................................1-2

DSP56300 Core Description ...........................................................................................1-3

DSP56367 Audio Processor Architecture........................................................................1-4

DSP56300 Core Functional Blocks .................................................................................1-5

Data ALU ....................................................................................................................1-5

Data ALU Registers...............................................................................................1-5

Multiplier-Accumulator (MAC) ...............................................................................1-6

Address Generation Unit (AGU) .................................................................................1-6

Program Control Unit (PCU).......................................................................................1-6

Internal Buses ............................................................................................................1-7

Direct Memory Access (DMA) ....................................................................................1-8

PLL-based Clock Oscillator ........................................................................................1-8

JTAG TAP and OnCE Module....................................................................................1-8

On-Chip Memory ........................................................................................................1-9

Off-Chip Memory Expansion ......................................................................................1-9

Peripheral Overview ......................................................................................................1-10

Host Interface (HDI08)..............................................................................................1-10

General Purpose Input/Output (GPIO) .....................................................................1-11

Triple Timer (TEC)....................................................................................................1-11

Enhanced Serial Audio Interface (ESAI) ..................................................................1-11

Enhanced Serial Audio Interface 1 (ESAI_1) ...........................................................1-11

Serial Host Interface (SHI)........................................................................................1-12

Digital Audio Transmitter (DAX) ...............................................................................1-12

CHAPTER 2

SIGNAL / CONNECTION DESCRIPTIONS 1

2.1

2.1.1

2.2

2.3

2.4

2.5

2.5.1

2.5.2

2.5.3

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

Signal Groupings .............................................................................................................2-2

Power Requirements ..................................................................................................2-3

Power ..............................................................................................................................2-5

Ground.............................................................................................................................2-6

Clock and PLL .................................................................................................................2-7

External Memory Expansion Port (Port A).......................................................................2-7

External Address Bus .................................................................................................2-7

External Data Bus.......................................................................................................2-8

External Bus Control...................................................................................................2-8

Interrupt and Mode Control............................................................................................2-10

Parallel Host Interface (HDI08)......................................................................................2-12

Serial Host Interface ......................................................................................................2-18

Enhanced Serial Audio Interface ...................................................................................2-21

Enhanced Serial Audio Interface_1 ...............................................................................2-27

SPDIF Transmitter Digital Audio Interface ....................................................................2-30

Timer .............................................................................................................................2-31

JTAG/OnCE Interface....................................................................................................2-31

MOTOROLA

DSP56367 24-Bit Digital Signal Processor User’s Manual

TOC-1

Table of Contents

Paragraph

Number

Page

Number

CHAPTER 3

SPECIFICATIONS

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.10.1

3.10.2

3.10.3

3.11

3.12

3.13

3.13.1

3.14

3.15

3.16

3.17

3.18

Introduction ..................................................................................................................... 3-2

Maximum Ratings ........................................................................................................... 3-2

Thermal Characteristics .................................................................................................. 3-3

DC Electrical Characteristics .......................................................................................... 3-4

AC Electrical Characteristics........................................................................................... 3-5

Internal Clocks ................................................................................................................ 3-6

External Clock Operation ................................................................................................ 3-7

Phase Lock Loop (PLL) Characteristics.......................................................................... 3-8

Reset, Stop, Mode Select, and Interrupt Timing ............................................................. 3-9

External Memory Expansion Port (Port A) .................................................................... 3-16

SRAM Timing........................................................................................................... 3-16

DRAM Timing .......................................................................................................... 3-20

Arbitration Timings................................................................................................... 3-37

Parallel Host Interface (HDI08) Timing ......................................................................... 3-38

Serial Host Interface SPI Protocol Timing..................................................................... 3-46

Serial Host Interface (SHI) I

C Protocol Timing............................................................ 3-53

Programming the Serial Clock ................................................................................. 3-55

Enhanced Serial Audio Interface Timing....................................................................... 3-57

Digital Audio Transmitter Timing................................................................................... 3-62

Timer Timing ................................................................................................................. 3-63

GPIO Timing ................................................................................................................. 3-63

JTAG Timing ................................................................................................................. 3-65

CHAPTER 4

DESIGN CONSIDERATIONS

4.1

4.2

4.3

4.4

4.4.1

Thermal Design Considerations...................................................................................... 4-2

Electrical Design Considerations .................................................................................... 4-3

Power Consumption Considerations............................................................................... 4-4

PLL Performance Issues................................................................................................. 4-5

Input (EXTAL) Jitter Requirements............................................................................ 4-5

CHAPTER 5

MEMORY CONFIGURATION

5.1

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.2

Data and Program Memory Maps................................................................................... 5-2

Reserved Memory Spaces ...................................................................................... 5-13

Program ROM Area Reserved for Motorola Use ..................................................... 5-13

Bootstrap ROM ........................................................................................................ 5-13

Dynamic Memory Configuration Switching .............................................................. 5-13

External Memory Support ........................................................................................ 5-14

Internal I/O Memory Map .............................................................................................. 5-15

TOC-2

DSP56367 24-Bit Digital Signal Processor User’s Manual

MOTOROLA

DSPD56367AG150 Related Products

	DSPD56367AG150	DSPD56367PV150	DSPC56367PV150	DSPB56367AG150
Description	24-BIT, 150 MHz, OTHER DSP, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144	24-BIT, 150MHz, OTHER DSP, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144	24-BIT, 150 MHz, OTHER DSP, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144	24-BIT, 150 MHz, OTHER DSP, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
Parts packaging code	QFP	QFP	QFP	QFP
package instruction	LFQFP,	20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144	LFQFP,	LFQFP,
Contacts	144	144	144	144
Reach Compliance Code	unknown	unknown	unknown	unknown
Address bus width	18	18	18	18
barrel shifter	YES	YES	YES	YES
boundary scan	YES	YES	YES	YES
maximum clock frequency	150 MHz	150 MHz	150 MHz	150 MHz
External data bus width	24	24	24	24
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144
length	20 mm	20 mm	20 mm	20 mm
low power mode	YES	YES	YES	YES
Number of terminals	144	144	144	144
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage	1.89 V	1.89 V	1.89 V	1.89 V
Minimum supply voltage	1.71 V	1.71 V	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
width	20 mm	20 mm	20 mm	20 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER

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