DSP96002FE60 datasheet, PDF - EEWORLD Datasheet

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DSP96002FE60: Description32-BIT, 60MHz, OTHER DSP, CQFP240, CERAMIC, QFP-240; CategoryThe embedded processor and controller Microcontrollers and processors; File Size696KB，111 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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DSP96002FE60 Overview

32-BIT, 60MHz, OTHER DSP, CQFP240, CERAMIC, QFP-240

DSP96002FE60 Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	QFP
package instruction	FQFP,
Contacts	240
Reach Compliance Code	unknown
Is Samacsys	N
Address bus width	32
barrel shifter	NO
boundary scan	NO
maximum clock frequency	60 MHz
External data bus width	32
Format	FLOATING POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-CQFP-G240
length	31.305 mm
low power mode	YES
Number of terminals	240
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Certification status	Not Qualified
Maximum seat height	4.15 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	HCMOS
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	31.305 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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DSP96002/D, Rev. 2

DSP96002

32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT

PROCESSOR

The DSP96002 is designed to support intensive graphic image and numeric processing. It is

a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024

words of data RAM (equally divided into X data and Y data memory), 1024 words of full-

speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)

controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug

circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units

operating in parallel. The DSP96002 has two identical memory expansion ports with control

lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and

Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which

facilitates easy interface with other processors for multiprocessor applications. Linear arrays

of DSP96002s can be implemented without glue logic. The MPU-style programming model

and instruction set allow straightforward generation of efficient, compact code. The high

speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive

applications that require floating-point processing and access to large memory subsystems.

Control

Freescale Semiconductor, Inc...

Bus

Control

Address

Generation

Unit (AGU)

YAB *

XAB *

PAB *

Program *

X Data *

Memory

1024

32 512

RAM and

RAM

Bootstrap

512

32†

ROM

Instruction

Cache

DDB

YDB

XDB

PDB

GDB

Y Data *

Memory

512

RAM

512

32†

ROM

Bus

Control

Address

External

Address

Switch

Dual Channel

DMA

Controller

Internal

Switch And Bit

Manipulation

Unit

External Address

Address

Switch

Port B

Data

AA0306

Port A

32-bit

Host

Interface

Timer

External

Data

Bus

Switch

32-bit

Host

Interface

Timer

External

Data

Bus

Switch

Data

Clock

Generator

Program

Decode

Controller

Program

Address

Generator

Program Controller

Program

Interrupt

Controller

OnCE

Data ALU

Debug

• IEEE Floating Point Controller

• 32

32 Integer ALU

Serial Debug

Port

CLK

32-bit Buses

* Dual Access (DMA/Core)

† 1024

32 Virtual Locations

MODC/IRQC

MODB/IRQB

MODA/IRQA

RESET

Figure 1

Block Diagram

For More Information On This Product,

Go to: www.freescale.com

DSP96002FE60 Related Products

	DSP96002FE60	DSP96002RC33	DSP96002RC40	DSP96002RC60	DSP96002FE40
Description	32-BIT, 60MHz, OTHER DSP, CQFP240, CERAMIC, QFP-240	IC,DSP,32-BIT,CMOS,PGA,223PIN,PLASTIC	IC,DSP,32-BIT,CMOS,PGA,223PIN,PLASTIC	32-BIT, 60MHz, OTHER DSP, PPGA223, PLASTIC, PGA-223	IC,DSP,32-BIT,CMOS,QFP,240PIN,CERAMIC
Parts packaging code	QFP	PGA	PGA	PGA	QFP
package instruction	FQFP,	PGA,	PGA,	PGA,	FQFP,
Contacts	240	223	223	223	240
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
Address bus width	32	32	32	32	32
barrel shifter	NO	NO	NO	NO	NO
boundary scan	NO	NO	NO	NO	NO
maximum clock frequency	60 MHz	33.3 MHz	40 MHz	60 MHz	40 MHz
External data bus width	32	32	32	32	32
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-CQFP-G240	S-PPGA-P223	S-PPGA-P223	S-PPGA-P223	S-CQFP-G240
length	31.305 mm	47.244 mm	47.244 mm	47.244 mm	31.305 mm
low power mode	YES	YES	YES	YES	YES
Number of terminals	240	223	223	223	240
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED
encapsulated code	FQFP	PGA	PGA	PGA	FQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, FINE PITCH	GRID ARRAY	GRID ARRAY	GRID ARRAY	FLATPACK, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.15 mm	3.81 mm	3.81 mm	3.81 mm	4.15 mm
Maximum supply voltage	5.25 V	5.5 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.5 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	NO	NO	YES
technology	HCMOS	HCMOS	HCMOS	HCMOS	HCMOS
Terminal form	GULL WING	PIN/PEG	PIN/PEG	PIN/PEG	GULL WING
Terminal pitch	0.5 mm	2.54 mm	2.54 mm	2.54 mm	0.5 mm
Terminal location	QUAD	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	QUAD
width	31.305 mm	47.244 mm	47.244 mm	47.244 mm	31.305 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1	1	1	1	1
ECCN code	-	3A991.A.2	-	3A001.A.3	3A991.A.2

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