D750MNT1B datasheet, PDF - EEWORLD Datasheet

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D750MNT1B: DescriptionMicroprocessor, 32-Bit, 750MHz, CMOS, MODULE CARD; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，84 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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D750MNT1B Overview

Microprocessor, 32-Bit, 750MHz, CMOS, MODULE CARD

D750MNT1B Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	MODULE
package instruction	MODULE CARD
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Is Samacsys	N
Address bus width	15
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	X-XXMA-X
low power mode	YES
Package body material	UNSPECIFIED
Package shape	UNSPECIFIED
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
speed	750 MHz
Nominal supply voltage	1.8 V
surface mount	NO
technology	CMOS
Terminal form	UNSPECIFIED
Terminal location	UNSPECIFIED
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Preliminary Information

AMD Duron

Processor

Data Sheet

Publication #

23802

Rev:

Issue Date:

September 2000

Preliminary Information

23802E—September 2000

AMD Duron™ Processor Data Sheet

Contents

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

2.1

2.2

2.3

2.4

AMD Duron™ Processor Microarchitecture Summary . . . . . 2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 11

Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

AMD Duron Processor Interface Signal Groupings . . . . . . . 19

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 20

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 20

VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 21

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SYSCLK and SYSCLK# DC and AC Characteristics . . . . . . 22

AMD System Bus Pins AC and DC Characteristics . . . . . . . . 25

AMD System Bus AC Characteristics . . . . . . . . . . . . . . . . . . . 26

General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 27

APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 28

Contents

iii

Preliminary Information

AMD Duron™ Processor Data Sheet

23802E—September 2000

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . .31

7.1

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Sequence and Timing Description . . . . . . . . . . . . . . .

Clock Multiplier Selection (FID[3:0]). . . . . . . . . . . . . . . . . . .

Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . .

The AMD Duron™ Processor and Northbridge Reset Pins .

7.2

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

8.1

8.2

8.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . . 39

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKIN, RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . . . .

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . .

DBRDY and DBREQ# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

K7CLKOUT and K7CLKOUT# Pins . . . . . . . . . . . . . . . . . . . .

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SADDIN[1]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . .

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

9.1

9.2

9.3

Contents

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