Data Sheet
January 2002
DSP1629 Digital Signal Processor
1 Features
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Optimized for mobile communications applications
with a bit manipulation unit for higher coding effi-
ciency.
On-chip, programmable, PLL clock synthesizer.
10 ns and 16.7 ns instruction cycle times at 3.0 V,
and 19.2 ns and 12.5 ns instruction cycle times at
2.7 V.
Mask-programmable memory map option: the
DSP1629x16 features 16 Kwords on-chip dual-port
RAM. The DSP1629x10 features 10 Kwords on-
chip dual-port RAM. Both feature 48 Kwords on-
chip ROM with a secure option.
Low power consumption:
— <1.9 mW/MIPS typical at 2.7 V.
Flexible power management modes:
— Standard sleep: 0.2 mW/MIPS at 2.7 V.
— Sleep with slow internal clock: 0.7 mW at 2.7 V.
— Hardware STOP (pin halts DSP): <20
µA.
Mask-programmable clock options: small signal
and CMOS.
100-TQFP package, providing excellent second-
level reliability.
Sequenced accesses to X and Y external memory.
Object code and pin compatible with the DSP1627.
Single-cycle squaring.
16 x 16-bit multiplication and 36-bit accumulation in
one instruction cycle.
Instruction cache for high-speed, program-efficient,
zero-overhead looping.
Dual 25 Mbits/s serial I/O ports with multiprocessor
capability:
— 16-bit data channel, 8-bit protocol channel.
8-bit parallel host interface:
— Supports 8-bit or 16-bit transfers.
—
Motorola
®
or
Intel
®
compatible.
8-bit control I/O interface.
256 memory-mapped I/O ports.
Supported by DSP1629 software and hardware
development tools.
2 Description
The DSP1629 is Agere Systems Inc.’s first digital signal
processor offering 100 MIPS operation at 3.0 V and
80 MIPS operation at 2.7 V with a reduction in power
consumption. Designed specifically for applications re-
quiring low power dissipation in
mobile communica-
tions
systems, the DSP1629 is a signal-coding device
that can be programmed to perform a wide variety of
fixed-point signal processing functions. The device is
based on the DSP1600 core with a bit manipulation unit
for enhanced signal coding efficiency. The DSP1629 in-
cludes a mix of peripherals specifically intended to sup-
port processing-intensive but cost-sensitive
applications in the area of digital wireless communica-
tions.
The DSP1629x16 contains 16 Kwords of internal dual-
port RAM (DPRAM), which allows simultaneous access
to two RAM locations in a single instruction cycle. The
DSP1629x10 supports the use of 10 Kwords of
DPRAM. Both devices contain 48 Kwords of internal
ROM (IROM).
The DSP1629 is object code compatible with the
DSP1627 while providing more memory. The DSP1629
is pin compatible with the DSP1627. Note that TRST
(JTAG test reset) replaces a V
DD
pin.
The DSP1629 supports 2.7 V and 3.0 V operation and
features flexible power management modes. Several
control mechanisms achieve low-power operation, in-
cluding a STOP pin for placing the DSP into a fully stat-
ic, halted state, and a programmable power control
register used to power down unused on-chip I/O units.
These power management modes allow for trade-offs
between power reduction and wake-up latency require-
ments. During system standby, power consumption is
reduced to less than 20
µA.
The on-chip clock synthesizer can be driven by an ex-
ternal clock whose frequency is a fraction of the instruc-
tion rate.
The device is packaged in a 144-pin PBGA, a 100-pin
BQFP, or a 100-pin TQFP, and is available with 10 ns
and 16.7 ns instruction cycle times at 3.0 V, and 19.2 ns
and 12.5 ns instruction cycle times at 2.7 V.
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IEEE
®
P1149.1 test port (JTAG boundary scan).
Full-speed in-circuit emulation hardware develop-
ment system on-chip.
DSP1629 Digital Signal Processor
Data Sheet
January 2002
Table of Contents
Contents
1
2
3
4
Page
Contents
Page
Features.............................................................. 1
Description .......................................................... 1
Pin Information.................................................... 3
Hardware Architecture ........................................ 8
4.1
DSP1629 Architectural Overview ............. 8
4.2
DSP1600 Core Architectural Overview .. 11
4.3
Interrupts and Trap ................................. 12
4.4
Memory Maps and Wait-States .............. 17
4.5
External Memory Interface (EMI)............ 20
4.6
Bit Manipulation Unit (BMU) ................... 21
4.7
Serial I/O Units (SIOs) ............................ 21
4.8
Parallel Host Interface (PHIF)................. 23
4.9
Bit Input/Output Unit (BIO)...................... 24
4.10 Timer ...................................................... 25
4.11 JTAG Test Port....................................... 25
4.12 Clock Synthesis ...................................... 27
4.13 Power Management ............................... 30
5 Software Architecture ....................................... 37
5.1
Instruction Set......................................... 37
5.2
Register Settings .................................... 46
5.3
Instruction Set Formats .......................... 56
6 Signal Descriptions ........................................... 62
6.1
System Interface..................................... 62
6.2
External Memory Interface ..................... 64
6.3
Serial Interface #1 .................................. 65
6.4
Parallel Host Interface or Serial
Interface #2 and Control I/O Interface .... 66
6.5
Control I/O Interface ............................... 66
6.6
JTAG Test Interface ............................... 67
7 Mask-Programmable Options ........................... 68
7.1
Input Clock Options ................................ 68
7.2
Memory Map Options ............................. 68
7.3
ROM Security Options............................ 68
8 Device Characteristics ...................................... 69
8.1
Absolute Maximum Ratings.................... 69
8.2
Handling Precautions ............................. 69
8.3
Recommended Operating Conditions .... 69
8.4
Package Thermal Considerations .......... 70
9 Electrical Characteristics and Requirements .... 71
9.1
Power Dissipation................................... 74
10 Timing Characteristics for 3.0 V Operation ....... 76
10.1 DSP Clock Generation
(3.0 V Operation) .................................... 77
10.2 Reset Circuit (3.0 V Operation)............... 78
10.3 Reset Synchronization (3.0 V Operation) 79
10.4 JTAG I/O Specifications
(3.0 V Operation) .................................... 80
10.5 Interrupt (3.0 V Operation)...................... 81
10.6 Bit Input/Output (BIO)
(3.0 V Operation) .................................... 82
10.7 External Memory Interface
(3.0 V Operation) .................................... 83
10.8 PHIF Specifications (3.0 V Operation).... 87
10.9 Serial I/O Specifications
(3.0 V Operation) .................................... 93
10.10 Multiprocessor Communication
(3.0 V Operation) .................................... 98
11 Timing Characteristics for 2.7 V Operation ....... 99
11.1 DSP Clock Generation
(2.7 V Operation) .................................. 100
11.2 Reset Circuit (2.7 V Operation)............. 101
11.3 Reset Synchronization
(2.7 V Operation) .................................. 102
11.4 JTAG I/O Specifications
(2.7 V Operation) .................................. 103
11.5 Interrupt (2.7 V Operation).................... 104
11.6 Bit Input/Output (BIO)
(2.7 V Operation) .................................. 105
11.7 External Memory Interface
(2.7 V Operation) .................................. 106
11.8 PHIF Specifications (2.7 V Operation).. 110
11.9 Serial I/O Specifications
(2.7 V Operation) .................................. 116
11.10 Multiprocessor Communication
(2.7 V Operation) .................................. 121
12 Outline Diagrams ............................................ 122
12.1 100-Pin BQFP (Bumpered Quad
Flat Pack).............................................. 122
12.2 100-Pin TQFP (Thin Quad Flat Pack)... 123
12.3 144-Pin PBGA (Plastic Ball Grid Array) 124
2
Agere Systems Inc.
FPGA/CPLD
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