NT2GC64B88B0NF-BE datasheet, PDF

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NT2GC64B88B0NF-BE: DescriptionDDR DRAM Module, 256MX64, 0.3ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, UDIMM-240; Categorystorage storage; File Size503KB，25 Pages; ManufacturerNanya; Websitehttp://www.nanya.com/cn; Environmental Compliance; Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.

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NT2GC64B88B0NF-BE Overview

DDR DRAM Module, 256MX64, 0.3ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, UDIMM-240

NT2GC64B88B0NF-BE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nanya
Parts packaging code	DIMM
package instruction	DIMM, DIMM240,40
Contacts	240
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.3 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	533 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
JESD-609 code	e4
length	133.35 mm
memory density	17179869184 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	240
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256MX64
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	30.05 mm
self refresh	YES
Maximum standby current	0.033 A
Maximum slew rate	2.59 mA
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	30 mm
Base Number Matches	1

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NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF

1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64

PC3-8500 / PC3-10600

Unbuffered DDR3 SDRAM DIMM

Based on DDR3-1066/1333 128Mx16 (1GB) / 256Mx8 (2GB/4GB) SDRAM B-Die

Features

•Performance:

Speed Sort

DIMM CAS Latency

fck – Clock Freqency

tck – Clock Cycle

fDQ – DQ Burst Freqency

PC3-8500

-BE

533

1.875

1066

PC3-10600

-CG

667

1.5

1333

MHz

Mbps

• Programmable Operation:

- DIMM



Latency: 6,7,8,9

- Burst Type: Sequential or Interleave

- Burst Length: BC4, BL8

- Operation: Burst Read and Write

• Two different termination values (Rtt_Nom & Rtt_WR)

• 14/10/1 (row/column/rank) Addressing for 1GB

• 14/10/1 (row/column/rank) Addressing for 2GB

• 15/10/2 (row/column/rank) Addressing for 4GB

• Extended operating temperature rage

• Auto Self-Refresh option

• Serial Presence Detect

• Gold contacts

•1GB: SDRAMs are in 96-ball BGA Package

• 2GB: SDRAMs are in 78-ball BGA Package

• 4GB: SDRAMs are in 78-ball BGA Package

• RoHS compliance and Halogen free

Unit

• 240-Pin Dual In-Line Memory Module (UDIMM)

• 128Mx64 (1GB) / 256Mx64 (2GB) / 512Mx64 (4GB) DDR3

Unbuffered DIMM based on 256Mx8 DDR3 SDRAM B-Die

devices.

• Intended for 533MHz/667MHz applications

• Inputs and outputs are SSTL-15 compatible

• V

= V

DDQ

= 1.5V ±0.075V

• SDRAMs have 8 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• DRAM DLL aligns DQ and DQS transitions with clock transitions.

• Address and control signals are fully synchronous to positive

clock edge

• Nominal and Dynamtic On-Die Termination support

• Halogen free product

Description

NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GC64B8HB0NF are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered

Dual In-Line Memory Module (UDIMM), organized as one rank of 128Mx64 (1GB) / 256Mx64 (2GB) and two ranks of 512Mx64 (4GB)

high-speed memory array. Modules use four 128Mx16 (1GB) 96-ball BGA packaged devices and eight 256Mx8 (2GB) 78-ball BGA

packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices . These DIMMs are manufactured using raw cards developed

for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All

NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.

The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of

1066Mbps/1333Mbps. Prior to any access operation, the device



latency and burst/length/operation type must be programmed into the

DIMM by address inputs A0-A13 (1GB/2GB) / A0-A14 (4GB) and I/O inputs BA0~BA2 using the mode register set cycle.

The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data

are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

REV 0.1

01/2010

NANYA reserves the right to change products and specifications without notice.

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