EE PLD, 18ns, 512-Cell, CMOS, PBGA256, BGA-256
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | AMD |
| Parts packaging code | BGA |
| package instruction | LBGA, BGA256,20X20,50 |
| Contacts | 256 |
| Reach Compliance Code | unknown |
| Is Samacsys | N |
| Other features | PAL BLOCKS INTERCONNECTED BY PIA; SHARED INPUT/CLOCK; 4 EXTERNAL CLOCKS; IN-SYSTEM PROGRAMMABLE |
| maximum clock frequency | 71 MHz |
| In-system programmable | YES |
| JESD-30 code | S-PBGA-B256 |
| JESD-609 code | e0 |
| JTAG BST | YES |
| length | 27 mm |
| Dedicated input times | |
| Number of I/O lines | 192 |
| Number of macro cells | 512 |
| Number of terminals | 256 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| organize | 0 DEDICATED INPUTS, 192 I/O |
| Output function | MACROCELL |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | LBGA |
| Encapsulate equivalent code | BGA256,20X20,50 |
| Package shape | SQUARE |
| Package form | GRID ARRAY, LOW PROFILE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| Programmable logic type | EE PLD |
| propagation delay | 18 ns |
| Certification status | Not Qualified |
| Maximum seat height | 1.65 mm |
| Maximum supply voltage | 5.25 V |
| Minimum supply voltage | 4.75 V |
| Nominal supply voltage | 5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | BALL |
| Terminal pitch | 1.27 mm |
| Terminal location | BOTTOM |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 27 mm |
| Base Number Matches | 1 |
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