S29AL016J70BFN043 datasheet, PDF

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S29AL016J70BFN043: DescriptionFlash, 1MX16, 70ns, PBGA48, FPBGA-48; Categorystorage storage; File Size786KB，58 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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S29AL016J70BFN043 Overview

Flash, 1MX16, 70ns, PBGA48, FPBGA-48

S29AL016J70BFN043 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	VFBGA, BGA48,6X8,32
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
Maximum access time	70 ns
Other features	BOTTOM BOOT BLOCK
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B48
JESD-609 code	e1
length	8.15 mm
memory density	16777216 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of departments/size	1,2,1,31
Number of terminals	48
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	1MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA48,6X8,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
switch bit	YES
type	NOR TYPE
width	6.15 mm
Base Number Matches	1

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S29AL016J

16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 3 V

Boot Sector Flash

Distinctive Characteristics

Architectural Advantages



Single Power Supply Operation

– Full voltage range: 2.7 to 3.6 volt read and write operations for

battery-powered applications



Manufactured on 110 nm Process Technology

– Fully compatible with 200 nm S29AL016D



Secured Silicon Sector region

– 128-word/256-byte sector for permanent, secure identification

through an 8-word/16-byte random Electronic Serial Number

accessible through a command sequence

– May be programmed and locked at the factory or by the customer



Flexible Sector Architecture

– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte

sectors (byte mode)

– One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32

Kword sectors (word mode)



Sector Group Protection Features

– A hardware method of locking a sector to prevent any program or

erase operations within that sector

– Sectors can be locked in-system or via programming equipment

– Temporary Sector Unprotect feature allows code changes in

previously locked sectors



Unlock Bypass Program Command

– Reduces overall programming time when issuing multiple program

command sequences



Top or Bottom Boot Block Configurations Available



Compatibility with JEDEC standards

– Pinout and software compatible with single-power supply Flash

– Superior inadvertent write protection

Performance Characteristics



High Performance

– Access times as fast as 55 ns

– Extended temperature range (–40°C to +125°C)



Ultra Low Power Consumption (typical values at 5 MHz)

– 0.2 µA Automatic Sleep mode current

– 0.2 µA standby mode current

– 7 mA read current

– 20 mA program/erase current



Cycling Endurance: 1,000,000 cycles per sector typical



Data Retention: 20 years typical

Package Options



48-ball Fine-pitch BGA



64-ball Fortified BGA



48-pin TSOP

Software Features



CFI (Common Flash Interface) Compliant

– Provides device-specific information to the system, allowing host

software to easily reconfigure for different Flash devices



Erase Suspend/Erase Resume

– Suspends an erase operation to read data from, or program data

to, a sector that is not being erased, then resumes the erase

operation



Data# Polling and Toggle Bits

– Provides a software method of detecting program or erase

operation completion

Hardware Features



Ready/Busy# Pin (RY/BY#)

– Provides a hardware method of detecting program or erase cycle

completion



Hardware Reset Pin (RESET#)

– Hardware method to reset the device to reading array data



WP# input pin

– For boot sector devices: at V

, protects first or last 16 Kbyte

sector depending on boot configuration (top boot or bottom boot)

Cypress Semiconductor Corporation

Document Number: 002-00777 Rev. *L

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised December 08, 2015

S29AL016J

General Description

The S29AL016J is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in

48-ball Fine-pitch BGA (0.8 mm pitch), 64-ball Fortified BGA (1.0 mm pitch) and 48-pin TSOP packages. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with

the standard system 3.0 volt V

supply. A 12.0 V V

or 5.0 V

are not required for write or erase operations. The device can also

be programmed in standard EPROM programmers.

The device offers access time of 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus

contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a

single 3.0 volt power supply

for both read and write functions. Internally generated and regulated

voltages are provided for the program and erase operations.

The S29AL016J is entirely command set compatible with the

JEDEC single-power-supply Flash standard.

Commands are written

to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine

that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the

Embedded Program

algorithm—an

internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The

Unlock Bypass

mode

facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the

Embedded Erase

algorithm—an internal

algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During

erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7

(Data# Polling) and DQ6 (toggle)

status bits.

After a program or erase cycle has been completed, the device is ready to read array

data or accept another command.

The

sector erase architecture

allows memory sectors to be erased and reprogrammed without affecting the data contents of other

sectors. The device is fully erased when shipped from the factory.

Hardware data protection

measures include a low V

detector that automatically inhibits write operations during power

transitions. The

hardware sector protection

feature disables both program and erase operations in any combination of the sectors

of memory. This can be achieved in-system or via programming equipment.

The

Erase Suspend/Erase Resume

feature enables the user to put erase on hold for any period of time to read data from, or

program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The

hardware RESET# pin

terminates any operation in progress and resets the internal state machine to reading array data. The

RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system

microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters

the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly reduced in

both these modes.

Spansion combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost

effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

Document Number: 002-00777 Rev. *L

Page 2 of 58

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