74FCT543CTSO datasheet, PDF - EEWORLD Datasheet

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74FCT543CTSO: DescriptionRegistered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SOIC-24; Categorylogic logic; File Size377KB，7 Pages; ManufacturerIDT (Integrated Device Technology)

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74FCT543CTSO Overview

Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SOIC-24

74FCT543CTSO Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	SOP, SOP24,.4
Contacts	24
Reach Compliance Code	not_compliant
Is Samacsys	N
Other features	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
Control type	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL
series	FCT
JESD-30 code	R-PDSO-G24
JESD-609 code	e0
length	15.418 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.064 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP24,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Prop。Delay @ Nom-Sup	5.3 ns
propagation delay (tpd)	7 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
translate	N/A
width	7.5 mm
Base Number Matches	1

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IDT74FCT543AT/CT/DT

FAST CMOS OCTAL LATCHED TRANSCEIVER

INDUSTRIAL TEMPERATURE RANGE

FAST CMOS

OCTAL LATCHED

TRANSCEIVER

FEATURES:

•

A, C, and D grades

Low input and output leakage

≤

1µA (max.)

CMOS power levels

True TTL input and output compatibility:

– V

= 3.3V (typ.)

– V

= 0.3V (typ.)

High Drive outputs (-15mA I

, 64mA I

)

Meets or exceeds JEDEC standard 18 specifications

Power off disable outputs permit "live insertion"

Available in SOIC and QSOP packages

IDT74FCT543AT/CT/DT

DESCRIPTION:

The FCT543T is a non-inverting octal transceiver built using an advanced

dual metal CMOS technology. This device contains two sets of eight D-type

latches with separate input and output controls for each set. For data flow

from A to B, for example, the A-to-B Enable (CEAB) input must be low in order

to enter data from A

–A

or to take data from B

–B

, as indicated in the

Function Table. With

CEAB

low, a low signal on the A-to-B Latch Enable

(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-

high transition of the

LEAB

signal puts the A latches in the storage mode and

their outputs no longer change with the A inputs. With

CEAB

and

OEAB

both

low, the 3-state B output buffers are active and reflect the data present at the

output of the A latches. Control of data from B to A is similar, but uses the

CEBA, LEBA

and

OEBA

inputs.

•

FUNCTIONAL BLOCK DIAGRAM

DETAIL A

DETAIL A x 7

OEBA

OEAB

CEBA

LEBA

CEAB

LEAB

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

OCTOBER 2008

DSC-5489/6

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Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	SOP, SOP24,.4	SOP, SOP24,.4	SOP, SOP24,.4	SSOP, SSOP24,.24	SSOP, SSOP24,.24	SSOP, SSOP24,.24
Contacts	24	24	24	24	24	24
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
Other features	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
Control type	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
series	FCT	FCT	FCT	FCT	FCT	FCT
JESD-30 code	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
JESD-609 code	e0	e0	e0	e0	e0	e0
length	15.418 mm	15.418 mm	15.418 mm	8.661 mm	8.661 mm	8.661 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.064 A	0.064 A	0.064 A	0.064 A	0.064 A	0.064 A
Humidity sensitivity level	1	1	1	1	1	1
Number of digits	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1
Number of ports	2	2	2	2	2	2
Number of terminals	24	24	24	24	24	24
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SSOP	SSOP	SSOP
Encapsulate equivalent code	SOP24,.4	SOP24,.4	SOP24,.4	SSOP24,.24	SSOP24,.24	SSOP24,.24
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Sup	5.3 ns	6.5 ns	4.4 ns	5.3 ns	4.4 ns	6.5 ns
propagation delay (tpd)	7 ns	8 ns	5 ns	7 ns	5 ns	8 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.65 mm	2.65 mm	2.65 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	0.635 mm	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
translate	N/A	N/A	N/A	N/A	N/A	N/A
width	7.5 mm	7.5 mm	7.5 mm	3.9116 mm	3.9116 mm	3.9116 mm
Base Number Matches	1	1	1	1	1	-
Maker	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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