4Mx8/2Mx16/1Mx32, 15 - 35ns, ZIP/SIMM
30A147-00
E
32 Megabit CMOS SRAM
DESCRIPTION:
The DPS1MX32ML/DPS1MX32MW is a 1 Meg x 32 high density,
high-speed Static Random Access Memory (SRAM) module, intended
for high performance computers and digital signal processing
applications. The DPS1MX32ML/DPS1MX32MW is comprised of eight
1 Meg x 4 devices surface mounted on an epoxy laminate substrate.
PIN-OUT DIAGRAM
*
FEATURES:
•
1 Meg x 32, 2 Meg x 16 or 4 Meg x 8 Configuration
•
High Speed: 15, 17, 20, 25, 35ns
•
All Inputs and Ouputs TTL Compatible
•
Fully Static Operation; No Clock or Refresh Required
•
Equal Read Access and Write Cycle Time
•
Package Available:
72-Pin ZIP
72-Pin SIMM
PD0 = V
SS
PD1 = N.C.
PD2 = V
SS
PD3 = N.C.
PIN NAMES
A0 - A19
Address Inputs
I/O0 - I/O31
Data In/Out
CE0 - CE3
Chip Enables
PD0 - PD3
Density I.D. Pins
1
OE
Output Enable
WE
Write Enable
V
DD
Power (+5V)
V
SS
Ground
N.C.
No Connect
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
* Index SIMM = Notch
ZIP = Chamfer
30A147-00
REV. E
1
DPS1MX32ML/DPS1MX32MW
FUNCTIONAL BLOCK DIAGRAM
Dense-Pac Microsystems, Inc.
TRUTH TABLE
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
CEn
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
I/O Pin
HIGH-Z
HIGH-Z
D
OUT
D
IN
Supply
Current
Standby
Active
Active
Active
RECOMMENDED OPERATING RANGE
2
Symbol
V
DD
V
IH
V
IL
T
A
Characteristic
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Operating Temp.
Min. Typ.
Max. Unit
4.5 5.0
5.5
V
2.2
V
DD
+0.3 V
3
-0.5
0.8
V
0 +25
+70
°C
X = Don’t Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
IH
HIGH Voltage
V
IL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
-
V
I
OL
= 8.0mA
0.4 V
CAPACITANCE
5
:
T
A
= 25°C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
60
25
80
80
15
Unit
Condition
Symbol
T
STC
T
BIAS
V
DD
V
ID
ABSOLUTE MAXIMUM RATINGS
4
Parameter
Max.
Unit
Storage Temperature
-55 to +125
°C
Temperature Under Bias
-10 to + 85
°C
2
Supply Voltage
-0.5 to + 7.0
V
2
Input/Output Voltage
-0.5 to V
DD
+0.5 V
pF
V
IN
= 0V
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
V
OL
V
OH
Characteristics
Input Leakage Current
Output Leakage Current
Operating Supply Current
Full Standby
Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
, CEn = V
IH
CEn = V
IL
, f = max., I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or V
IN
≤
V
SS
+0.2V,
CEn
≥
V
DD
-0.2, f = 0mHz
CEn = V
IH
, f = max.
I
OUT
= 8.0mA
I
OUT
= -4.0mA
COMMERCIAL
Min.
Max.
Unit
µA
µA
mA
mA
mA
V
V
30A147-00
REV. E
-16
-10
+16
+10
1520
120
480
0.4
2.4
2
Dense-Pac Microsystems, Inc.
DPS1MX32ML/DPS1MX32MW
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
* Transition measured between 0.8V and 2.2V.
0V to 3.0V
5ns *
1.5V
Figure 1.
Output Load
** Including Probe and Jig Capacitance.
+5V
1480Ω
Output Load
Load
1
2
C
L
30pF
5pF
Parameters Measured
except t
CLZ
, t
CHZ
, t
WHZ
, t
OW
, t
OLZ
and t
OHZ
t
CLZ
, t
CHZ
, t
WHZ
, t
OW
D
OUT
C
L
**
225Ω
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
ACS
t
CLZ
t
OE
t
OLZ
t
CHZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in LOW-Z
5, 7
Output Enable to Output Valid
Output Enable to Output in LOW-Z
5, 7
Chip Enable to Output in HIGH-Z
5, 7
Output Enable to Output in HIGH-Z
5, 7
Output Hold from Address Change
15ns
15
15
15
5
8
0
0
0
5
7
7
0
0
0
5
5
8
7
7
0
0
0
5
17ns
17
17
17
5
10
9
9
0
0
0
5
20ns
20
20
20
5
12
10
10
0
0
0
5
25ns
25
25
25
5
12
12
12
35ns
35
35
35
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE:
Over operating ranges
8
No. Symbol
10
12
11
13
14
15
16
17
18
19
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Set-up Time ***
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
5, 7
Data to Write Time Overlap
Data Hold Time from Write Time
Output Active from End of Write
5, 7
15ns
15
12
12
0
12
3
0
8
0
3
17ns
17
12
12
0
12
3
0
8
0
5
20ns
20
15
15
0
15
3
0
10
0
5
25ns
25
17
17
0
17
3
0
12
0
5
35ns
35
20
20
0
20
3
0
15
0
5
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
9
10
15
*** Valid for both Read and Write Cycles.
30A147-00
REV. E
3
DPS1MX32ML/DPS1MX32MW
Dense-Pac Microsystems, Inc.
READ CYCLE 1:
Address Controlled. WE is HIGH. CE and OE are LOW.
ADDRESS
DATA I/O
READ CYCLE 2:
CE Controlled. WE is HIGH.
ADDRESS
OE
CE
DATA I/O
WRITE CYCLE 1:
WE Controlled..
8
ADDRESS
CE
WE
DATA IN
DATA OUT
4
30A147-00
REV. E
Dense-Pac Microsystems, Inc.
DPS1MX32ML/DPS1MX32MW
WRITE CYCLE 2:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTES:
1. The PD0 - PD3 pins are used to identify memory density when other density versions of the JEDEC STD module can be installed
in the same socket.
2. All voltages are with respect to V
SS
.
3. -2.0V min. for pulse width less than 20ns (V
IL
min.= -0.5V at DC level).
4. Stresses greater than those under
ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
5. This parameter is guaranteed and not 100% tested.
6. Transition is measured at the point of
±
500mV from steady state voltage.
7. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs
must not be applied.
8. The outputs are in a high impedance state when WE is LOW.
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A147-00
REV. E
5
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