PRELIMINARY
CY7C1440V33
CY7C1442V33
CY7C1446V33
1M x 36/2M x 18/512K x 72
Pipelined SRAM
Features
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Fast clock speed: 250, 200, and 167 MHz
Provide high-performance 3-1-1-1 access rate
Fast access time: 2.7, 3.0 and 3.5 ns
Optimal for depth expansion
Single 3.3V –5% and +5% power supply V
DD
Separate V
DDQ
for 3.3V or 2.5V
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down for portable applications
High-density, high-speed packages
JTAG boundary scan for BGA packaging version
Available in 119-ball bump BG,165-ball FBGA package,
and 100-pin TQFP packages (CY7C1440V33 and
CY7C1442V33). 209 FBGA package for CY7C1446V33.
Chip Enable (CE), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWa, BWb, BWc, BWd, and BWE), and
Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQ
a,b,c,d
) and the data
parity (DP
a,b,c,d
) outputs, enabled by OE, are also
asynchronous.
DQ
a,b,c,d
and DP
a,b,c,d
apply to CY7C1440V33, DQ
a,b
and
DP
a,b
apply to CY7C1442V33, and DQ
a,b,c,d,e,f,g,h
and
DP
a,b,c,d,e,f,g,h
apply to CY7C1446V33. a,b,c,d,e,f,g,h each
are eight bits wide in the case of DQ and one bit wide in the
case of DP.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to eight bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc
controls DQc and DPd. BWd controls DQ and DPd. BWe
controls DQe and DPe. BWf controls DQf and DPf. BWg
controls DQg and DPg. BWh controls DQh and DPh. BWa,
BWb, BWc, BWd, BWe, BWf, BWg, and BWh can be active
only with BWE LOW. GW LOW causes all bytes to be written.
Write pass-through capability allows written data available at
the output for the immediately next Read cycle. This device
also incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
All inputs and outputs of the CY7C1440V33, CY7C1442V33,
and the CY7C1446V33 are JEDEC-standard JESD8-5
-compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1440V33, CY7C1442V33, and CY7C1446V33
SRAMs integrate 1,048,576 x 36/2,097,152 x 18 and 524,288
x 72 SRAM cells with advanced synchronous peripheral
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Selection Guide
[1]
CY7C1440V33
CY7C1446V33
CY7C1446V33
-300
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. Shaded areas contain advance information.
CY7C1440V33
CY7C1446V33
CY7C1446V33
-250
2.7
TBD
TBD
CY7C1440V33
CY7C1446V33
CY7C1446V33
-200
3.0
TBD
TBD
CY7C1440V33
CY7C1446V33
CY7C1446V33
-167
3.5
TBD
TBD
Unit
ns
mA
mA
2.3
Com’l
TBD
TBD
Cypress Semiconductor Corporation
Document #: 38-05184 Rev. *B
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3901 North First Street
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San Jose
,
CA 95134
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408-943-2600
Revised November 13, 2002
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