Freescale Semiconductor, Inc.
MPC2605/D
Rev. 12, 11/2002
Integrated Secondary Cache
for Microprocessors That
Implement PowerPC
Architecture
Freescale Semiconductor, Inc...
The MPC2605 is a single chip, 256KB integrated look-aside
cache with copy-back capability designed for applications
using a 60x bus. Using 0.38
µm
technology along with
standard cell logic technology, the MPC2605 integrates data,
tag, host interface, and least recently used (LRU) memory
with a cache controller to provide a 256KB, 512KB, or 1MB
Level 2 cache with one, two, or four chips on a 64-bit 60x
bus.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single Chip L2 Cache
66 or 83 MHz Zero Wait State Performance (2-1-1-1 Burst)
Four-Way Set Associative Cache Design
32K x 72 Data Memory Array
8K x 18 Tag Array
Address Parity Support
LRU Cache Control Logic
Copy-Back or Write-Through Modes of Operation
Copy-Back Buffer for Improved Performance
Single 3.3 V Power Supply
5 V Tolerant I/O
One-, Two-, or Four-Chip Cache Solution (256KB, 512KB, or 1MB)
Single Clock Operation
Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)
Supports up to Four Processors in a Shared Cache Configuration
High Board Density 25 mm 241 PBGA Package
ZP PACKAGE
PBGA
ZP PACKAGE
CASE 1138-0
PBGA
CASE 1138-01
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC2605/D
BLOCK DIAGRAM
COPY-BACK
BUFFER
CONTROL
RD/WR
60x BUS
INTERFACE
CONTROLLER
AND
BUS INTERFACE
A27, A28
8K x 72 x 4
DATA RAM
DH0 – DH31
DL0 – DL31
DP0 – DP7
A0 – A31
RD/WR
WAY SELECT
Freescale Semiconductor, Inc...
2K x 8 LRU
2K x 18 x 4
TAG RAM
COMPARE
2
Integrated Secondary Cache for Microprocessors
That Implement PowerPC Architecture
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
MPC2605/D
PIN ASSIGNMENT
1
A
B
C
D
E
TA
2
ABB
CPU3
BG
FDN
L2 BR
CFG4
3
L2 BG
4
DH20
5
6
7
8
9
DH27
DH28
V
SS
V
DD
10
11
12
DL19
DL20
DL21
V
SS
13
DL22
DL23
V
SS
V
SS
14
DP6
DL24
V
SS
15
DL25
DL26
V
DD
16
DL27
DL28
V
DD
17
DL29
DL31
AP3
AP0
18
DL30
DP7
AP2
APE
AP1
19
DH19 DH17 DH31 DH29
DH18 DH16 DH30
DH22
V
SS
V
SS
DP3
V
SS
DH26 DL16
DH25 DL17
DH24
V
DD
DL18
V
DD
DH23 DH21
L2
MISS INH
V
DD
DP2
CPU3 CPU3
BR
DBG
CPU2
BR
CPU2
DBG
L2
L2
CI
FLUSH
GBL
TSIZ2
A13
A16
A17
A21
A23
A26
A29
A12
A9
A6
A4
A2
Freescale Semiconductor, Inc...
F
G
H
J
K
L
M
L2 DBG CPU2
BG
CFG3 APEN
TSIZ1 TSIZ0
V
SS
V
SS
V
DD
V
DD
V
DD
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
V
DD
V
DD
V
SS
V
SS
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
A14
A19
A20
A25
A28
A31
A10
A7
V
SS
V
DD
DH5
DH4
V
SS
DH3
DH2
V
SS
DH1
DH0
V
SS
DP1
DH15
V
SS
DH14
DH13
DH12
V
DD
DH10
DH11
DH9
V
DD
DL1
DL0
DH8
V
DD
DL4
DL3
DL2
V
SS
V
SS
DL6
DL5
V
SS
V
SS
DP4
DL7
V
SS
DL10
DL8
V
DD
DL12
DL9
DP5
DL14
DL11
V
DD
V
DD
DL15
DL13
V
SS
A15
A18
A22
A24
A27
A30
A11
A8
A5
A3
A1
A0
CPU L2 CLAIM NC
DBG
ARTRY
TEA
CI
CPU
BR
AACK
WT
HRESET DBB PWRDN V
DD
TT1
TT4
TT3
TT0
TT2
TBST
TS
V
DD
V
DD
V
SS
CPU BG CLK
N
P
SRESET
TDI
L2 L2 UPDATE V
SS
TAG CLR INH
TCK
TRST
CPU4
DBG
CFG0
CFG1
DP0
TMS
NC
V
DD
V
DD
DH7
DH6
R
T
U
V
W
TDO
CPU4
BG
CPU4
BR
CFG2
TOP VIEW
MOTOROLA
Integrated Secondary Cache for Microprocessors
That Implement PowerPC Architecture
For More Information On This Product,
Go to: www.freescale.com
3
Freescale Semiconductor, Inc.
MPC2605/D
PIN DESCRIPTIONS
Pin Locations
19G, 17H – 19H, 17J – 19J,
17K – 19K, 17L – 19L,
17M – 19M, 17N – 19N,
17P – 19P, 17R – 19R,
18T, 19T, 18U, 19U, 18V,
19V, 18W *
3G
2A
17C – 19C, 17D*
Pin Name
A0 – A31
Type
I/O
Description
Address inputs from processor. Can also be outputs for processor
snoop addresses. A0 is the MSB. A31 is the LSB.
AACK
ABB
AP0 – AP3
APE
I/O
I/O
I/O
O
Address acknowledge input/output.
Used as an input to qualify bus grants. Driven as an output during
address tenure initiated by the MPC2605.
Address parity.
Address parity error. When an address parity error is detected, APE
will be driven low one clock cycle after the assertion of TS then
High-Z following clock cycle.
Address parity enable. When tied low, enables address parity bits
and the address parity error bit.
Address retry status I/O. Generated when a read or write snoop to a
dirty processor cache line has occurred.
Configuration inputs. These must be tied to either V
DD
or V
SS
.
CFG0
0
0
0
1
1
1
1
CFG3
CFG1
0
1
1
0
0
1
1
CFG2
0
0
1
0
1
0
1
256KB
512KB; A26 = 0
512KB; A26 = 1
1MB; A25 – A26 = 00
1MB; A25 – A26 = 01
1MB; A25 – A26 = 10
1MB; A25 – A26 = 11
Freescale Semiconductor, Inc...
19B
18E
1G
2U
2V
1V
17E
2B
APEN
ARTRY
CFG0
CFG1
CFG2
CFG3
CFG4
I
I/O
I
Snoop Data Tenure Selector
1 Any snoop cycle is address only,
even when TT3 = 1
0 TT3 will decide whether a snoop
is a data- or address-only tenure
AACK Driver Enable
0 Disable AACK driver
1 Enable AACK driver
CFG4
2G
3M
2M
3E
1B
1T
2H
CI
CLK
CPU BG
CPU2 BG
CPU3 BG
CPU4 BG
CPU BR
I/O
I
I
I
I
I
I
Cache inhibit I/O.
Clock input. This must be the same as the processor clock input.
CPU bus grant input.
MPC2605 logically ORs this signal with CPU BG. Used in
multiprocessor configuration as the second CPU BG.
MPC2605 logically ORs this signal with CPU BG. Used in
multiprocessor configuration as the third CPU BG.
MPC2605 logically ORs this signal with CPU BG. Used in
multiprocessor configuration as the fourth CPU BG.
CPU bus request input.
4
Integrated Secondary Cache for Microprocessors
That Implement PowerPC Architecture
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
MPC2605/D
PIN DESCRIPTIONS
(continued)
Pin Locations
2D
2C
1U
1F
3D
3C
Pin Name
CPU2 BR
CPU3 BR
CPU4 BR
CPU DBG
CPU2 DBG
CPU3 DBG
CPU4 DBG
DL0 – DL31
Type
I
I
I
I
I
I
I
I/O
Description
MPC2605 logically ORs this signal with CPU BR. Used in
multiprocessor configuration as the second CPU BR.
MPC2605 logically ORs this signal with CPU BR. Used in
multiprocessor configuration as the third CPU BR.
MPC2605 logically ORs this signal with CPU BR. Used in
multiprocessor configuration as the fourth CPU BR.
CPU data bus grant input from arbiter.
MPC2605 logically ORs this signal with CPU DBG. Used in
multiprocessor configuration as the second CPU DBG.
MPC2605 logically ORs this signal with CPU DBG. Used in
multiprocessor configuration as the third CPU DBG.
MPC2605 logically ORs this signal with CPU DBG. Used in
multiprocessor configuration as the fourth CPU DBG.
Data bus low input and output. DL0 is the MSB. DL31 is the LSB.
Freescale Semiconductor, Inc...
2T
11A – 13A, 15A – 18A,
11B – 17B, 11C, 12C, 10U,
11U, 10V – 12V, 14V – 17V,
11W – 17W *
4A – 10A, 4B – 10B, 6C,
10C, 8U, 9U, 3V – 6V,
8V, 9V, 3W – 10W*
2J
DH0 – DH31
I/O
Data bus high input and output. DH0 is the MSB. DH31 is the LSB.
DBB
I/O
Data bus busy. Used as input when processor is master, driven as
an output after a qualified L2 DBG when MPC2605 is the bus
master. Note: To operate in Fast L2 mode, this pin must be tied high.
Data bus parity input and output.
Flush done I/O used for communication between other MPC2605
devices. Must be tied together between all MPC2605 parts along
with a pullup resistor.
Global transaction. Always negated when MPC2604 is bus master.
Hard reset input from processor bus. This is an asynchronous input
that must be low for at least 16 clock cycles to ensure the MPC2605
is properly reset.
Bus grant input from arbiter.
Bus request I/O. Normally used as an output.
Secondary cache inhibit sampled, after assertion of TS. Assertion
prevents linefill.
L2 cache claim output. Used to claim the bus for processor initiated
memory operations that hit the L2 cache. L2 CLAIM goes true (low)
before the rising edge of CLK following TS true. Because this output
is not always driven, a pullup resistor may be necessary to ensure
proper system functioning.
Data bus grant input. Comes from system arbiter, used to start data
tenure for bus operations where MPC2605 is the bus master.
Causes cache to write back dirty lines and clears all tag valid bits.
14A, 18B, 5C, 8C,
16U, 7V, 13V, 2W *
1C
DP0 – DP7
FDN
I/O
I/O
19E
1J
GBL
HRESET
O
I
3A
1D
19D
2F
L2 BG
L2 BR
L2 CI
L2 CLAIM
I
I/O
I
O
2E
18D
L2 DBG
L2 FLUSH
I
I
MOTOROLA
Integrated Secondary Cache for Microprocessors
That Implement PowerPC Architecture
For More Information On This Product,
Go to: www.freescale.com
5
京公网安备 11010802033920号
EEWORLD
