November 1996
Revision 1.1
DATA SHEET
FSA4UN364(2/4)-(60/70)J(G/S)-S
16MByte (4M x 36) CMOS DRAM Module
General Description
The FSA4UN364(2/4)-(60/70)J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by
36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. FSA4UN3644 supports 4K refresh. FSA4UN3642
supports 2K refresh.
The module utilizes eight, Fujitsu MB811(7/6)400A-(60/70)PJ CMOS 4Mx4 and four 4Mx1 Fujitsu MB814100C-(60/70)PJ dynamic
RAMs in an SOJ package on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved
noise immunity.
Control lines provided are such that byte control is possible.
Features
• JEDEC standard pinout
• High Density: 16MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power:
6.05/5.39 W (max.) - 2K: Active (60/70 ns)
5.17/4.51 W (max.) - 4K: Active (60/70 ns)
132mW (max.) - Standby (TTL)
66mW (max.) - Standby (CMOS)
• TTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 5V±10%
• Height: 0.85"
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to V
SS
Power Dissipation
Operating Temperature
Storage Temperate
Short Circuit Output Current
Symbol
V
T
P
T
T
opr
T
stg
I
OS
Ratings
-1 to +7.0
12
0 to +70
-55 to +125
50
Unit
V
W
°
C
°
C
mA
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to +70
°C)
Symbol
V
CC
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High voltage
Input Low voltage
Min
4.5
0
2.4
-0.3
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1
0.8
Unit
V
V
V
V
Fujitsu Microelectronics, Inc.
1
November 1996
Revision 1.1
FSA4UN364(2/4)-(60/70)J(G/S)-S
Functional Diagram
CAS3*
CAS2*
CAS1*
CAS0*
RAS0*
4M x 9
Block
4M x 9
Block
4M x 9
Block
4M x 9
Block
V
CC
V
SS
Decoupling capacitors
to all devices
RAS2*
DQ0~DQ35
(All specifications of the device are subject to change without notice.)
Notes:
1.
2.
3.
4.
5.
“*” signifies active low signal.
Each 4Mx9 block comprises two 4Mx4 and one 4Mx1 DRAMs.
Addresses A0 ~ A10/A11: To all devices (A11 is NC for 2KR).
WE*: To all devices.
OEs* of all devices are grounded.
2
Fujitsu Microelectronics, Inc.
November 1996
Revision 1.1
FSA4UN364(2/4)-(60/70)J(G/S)-S
Pin Name
A0~A10†
A0~A11
A0~A9
DQ0~DQ35
CAS0*~CAS3*
RAS0*, RAS2*
Addresses for 2K Refresh Module
Row Addresses for 4K Refresh Module
Column Addresses for 4K Refresh Module
Data Inputs/Outputs
Column Address Strobes
Row Address Strobes
WE*
PD1~PD4
V
CC
V
SS
NC
Write Enable
Presence Detects
Power Supply
Ground
No Connection
Presence Detect Pins
Pin
PD1
PD2
PD3
PD4
-60
V
SS
NC
NC
NC
-70
V
SS
NC
V
SS
NC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Designation
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
V
CC
NC
A0
A1
A2
A3
A4
A5
A6
Pin No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin Designation
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11†
V
CC
A8
A9
NC
RAS2*
DQ26
DQ8
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Pin Designation
DQ17
DQ35
V
SS
CAS0*
CAS2*
CAS3*
CAS1*
RAS0*
NC
NC
WE*
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin Designation
DQ12
DQ30
DQ13
DQ31
V
CC
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
V
SS
†: A11 (pin 29) is NC for the 2K refresh module.
Fujitsu Microelectronics, Inc.
3
November 1996
Revision 1.1
FSA4UN364(2/4)-(60/70)J(G/S)-S
DC CHARACTERISTICS
(V
CC
= 5.0V±10%, V
SS
= 0V, T
A
= 0 to +70
°C)
60
Parameter
Symbol
Test Condition
Refresh
Min.
Operating Current
I
CC1
RAS*, CAS* cycling; t
RC
= min.
TTL Interface
RAS*, CAS* = V
IH
D
out
= HIgh-Z
CMOS Interface
RAS*, CAS*
≥
V
cc
- 0.2V
D
out
= HIgh-Z
CAS* = V
IH
; RAS*, Address
cycling @ t
RC
= min
RAS*, CAS* cycling @
t
RC
= min.
RAS* = V
IL
; CAS*, Address
cycling @ t
PC
= min
0V
≤
V
in
≤
V
CC
+0.5V
0V
≤
V
out
≤
V
CC
D
out
= Disable
I
OH
= -5 mA
I
OL
= 4.2 mA
2K
4K
2K
4K
2K
4K
2K
4K
-
-
-
Max.
1100
940
24
Min.
-
-
-
Max.
980
mA
820
24
mA
1, 2
70
Unit
Note
Standby current
I
CC2
-
-
-
-
-
-
-
-120
-10
2.4
-
12
1100
940
1100
940
860
780
120
10
-
0.4
-
-
-
-
-
-
-
-120
-10
2.4
-
12
980
mA
RAS* -only Refresh
Current
CAS*-before-RAS*
Refresh Current
Fast Page Mode
Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Notes:
1.
2.
3.
I
CC3
mA
820
980
mA
820
740
mA
660
120
10
-
0.4
2
I
CC4
I
CC5
I
LI
I
LO
V
OH
V
OL
1, 3
µ
A
µ
A
V
V
Values depend on load condition when the device is selected. Maximum Values are specified at the output open condition.
Address can be changed once or less while RAS* = V
IL
.
Address can be changed once or less while CAS* = V
IH
.
CAPACITANCE
(TA =+25°C, V
CC
= 5.0V±10%)
Parameter
Input Capacitance (Address)
Input Capacitance (RAS0*, RAS2*)
Input Capacitance (CAS0*~CAS3*)
Input Capacitance (WE*)
Input/Output Capacitance (DQ0~DQ31)
Notes:
1.
2.
Symbol
C
I1
C
I2
C
I3
C
I4
C
I/O
Max.
85
46
27
87
13
Unit
pF
pF
pF
pF
pF
Note
1
1
1
1
1, 2
Capacitance is measured with Boonton Meter or effective capacitance method.
CAS* = V
IH
to disable D
out
.
4
Fujitsu Microelectronics, Inc.
November 1996
Revision 1.1
FSA4UN364(2/4)-(60/70)J(G/S)-S
AC CHARACTERISTICS
(TA = 0 to +70°C, V
CC
= 5.0V±10%, V
SS
= 0V)
60
Parameter
Access time from column address
Access time from CAS* precharge
Column address set-up time
Row address set-up time
Access time from CAS*
Column address hold time
CAS* pulse width
CAS* hold time (CBR refresh)
CAS* precharge time (Fast page)
CAS* to RAS* precharge time
CAS* hold time
CAS* set-up time (CBR refresh)
Write command to CAS* lead time
Data-in hold time
Data-in set-up time
Output buffer turn-off time
Fast Page cycle time
Access time from RAS*
RAS* to column address delay time
Row address hold time
Column address to RAS* lead time
RAS* pulse width
RAS* pulse width (Fast Page cycle)
Random read/write cycle time
RAS* to CAS* delay time
Read command hold time to CAS*
Read command set-up time
(2048 cycles)
Refresh period
(4096 cycles)
RAS* hold time from CAS* precharge
RAS* precharge time
RAS* precharge to CAS* hold time
Read command hold time to RAS*
RAS* hold time
Write command to RAS* lead time
Transition time (rise and fall)
Write command hold time
Write command set-up time
Write command pulse width
Symbol
Min
t
AA
t
CPA
t
ASC
t
ASR
t
CAC
t
CAH
t
CAS
t
CHR
t
CP
t
CRP
t
CSH
t
CSR
t
CWL
t
DH
t
DS
t
OFF
t
PC
t
RAC
t
RAD
t
RAH
t
RAL
t
RASC
t
RAS
t
RC
t
RCD
t
RCH
t
RCS
t
REF
t
RHCP
t
RP
t
RPC
t
RRH
t
RSH
t
RWL
t
T
t
WCH
t
WCS
t
WP
-
-
0
0
-
15
15
10
10
0
60
0
15
15
0
-
40
-
15
10
30
60
-
110
20
0
0
-
-
35
40
5
0
15
15
3
15
0
15
Max
30
35
-
-
15
-
10000
-
-
-
-
-
-
-
-
15
-
60
30
-
-
100000
100000
-
45
-
-
32
64
-
-
-
-
-
-
50
-
-
-
Min
-
-
0
0
-
15
20
12
10
0
70
0
18
15
0
-
45
-
15
10
35
70
-
130
20
0
0
-
-
40
50
5
0
20
18
3
15
0
15
Max
35
40
-
-
20
-
10000
-
-
-
-
-
-
-
-
17
-
70
35
-
-
100000
100000
-
53
-
-
32
64
-
-
-
-
-
-
50
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
2
4
8
12
3, 4
10
9
9
6
1
1
3, 4, 5
3, 10
3, 11
70
Unit
Notes
Fujitsu Microelectronics, Inc.
5