GS8130237E-300 datasheet, PDF - EEWORLD Datasheet

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GS8130237E-300: DescriptionDDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165; Categorystorage storage; File Size669KB，34 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8130237E-300 Overview

DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165

GS8130237E-300 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Is Samacsys	N
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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Preliminary

GS81302D07/10/19/37E-400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

144Mb SigmaQuad

-II+

Burst of 4 SRAM

400 MHz–300 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaQuad™ Family Overview

The GS81302D07/10/19/37E are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302D07/10/19/37E SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS81302D07/10/19/37E SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ B4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers. Because the LSBs are

tied off internally, the address field of a SigmaQuad-II+ B4

RAM is always two address pins less than the advertised index

depth (e.g., the 8M x 18 has a 2M addressable index).

Parameter Synopsis

-400

tKHKH

tKHQV

2.5 ns

0.45 ns

-375

2.66 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.01 1/2010

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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