PRELIMINARY
CY7C1360A1/GVT71256DA36
CY7C1362A1/GVT71512DA18
256K x 36/512K x 18 Pipelined SRAM
Features
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Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
Fast clock speed: 225, 200, 166, and 150 MHz
Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V –5% and +10% power supply
3.3V or 2.5V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to V
SS
at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
Address pipeline capability
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
JTAG boundary scan for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package version
Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE
2
and
CE
2
), burst control inputs (ADSC, ADSP and ADV), Write En-
,
ables (BWa, BWb, BWc, BWd, and BWE), and global write
(GW). However, the CE
2
chip enable input is only available for
TA(GVTI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The CY7C1360A1/GVT71256DA36 and CY7C1362A1/
GVT71512DA18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
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Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The CY7C1360A1/GVT71256DA36 and CY7C1362A1/
GVT71512DA18 SRAMs integrate 262,144x36 and
524,288x18 SRAM cells with advanced synchronous periph-
Selection Guide
7C1360A1-225
71256DA36-4.4
7C1362A1-225
71512DA18-4.4
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
2.5
570
10
7C1360A1-200
71256DA36-5
7C1362A1-200
71512DA18-5
3.0
510
10
7C1360A1-166
71256DA36-6
7C1362A1-166
71512DA18-6
3.5
425
10
7C1360A1-150
71256DA36-6.7
7C1362A1-150
71512DA18-6.7
3.5
380
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Cypress Semiconductor Corporation
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3901 North First Street
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San Jose
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CA 95134
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408-943-2600
May 18, 2000
PRELIMINARY
256K X 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
Name
A0
A1
A
Type
Input-
Synchronous
CY7C1360A1/GVT71256DA36
CY7C1362A1/GVT71512DA18
Description
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses associ-
ated with A0 and A1, during burst cycle and wait cycle.
37
4P
36
4N
35, 34, 33, 32,
2A, 3A, 5A, 6A, 3B,
100, 99, 82, 81,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 3T, 4T, 5T 44, 45, 46, 47, 48,
49, 50
92 (T Version)
43 (TA Version)
5L
5G
3G
3L
4M
93
94
95
96
87
BWa
BWb
BWc
BWd
BWE
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and
HIGH for a READ cycle. BWa controls DQa. BWb con-
trols DQb. BWc controls DQc. BWd controls DQd. Data
I/O are high impedance if either of these inputs are LOW,
conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte write
operations and must meet the set-up and hold times
around the rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit
WRITE to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the
rising edge of CLK.
Clock: This signal registers the addresses, data, chip
enables, write control and burst control inputs on its ris-
ing edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP
.
Chip Enable: This active HIGH input is used to enable
the device.
Chip Enable: This active LOW input is used to enable the
device. Not available for B and T package versions.
Output Enable: This active LOW asynchronous input en-
ables the data output drivers.
Address Advance: This active LOW input is used to con-
trol the internal burst counter. A HIGH on this pin gener-
ates wait cycle (no address advance).
Address Status Processor: This active LOW input, along
with CE being LOW, causes a new external address to
be registered and a READ cycle is initiated using the new
address.
Address Status Controller: This active LOW input caus-
es device to be deselected or selected along with new
external address to be registered. A READ or WRITE
cycle is initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Input-
Synchronous
Input-
Synchronous
4H
88
GW
4K
89
CLK
Input-
Synchronous
4E
2B
98
97
CE
CE
2
CE
2
OE
ADV
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input
Input-
Synchronous
Input-
Synchronous
- (not available for PB- 92 (for TA Version
GA)
only)
4F
4G
86
83
4A
84
ADSP
4B
85
ADSC
Input-
Synchronous
3R
31
MODE
Input-
Static
7T
64
ZZ
Input-
Snooze: This active HIGH input puts the device in low
Asynchronous power consumption standby mode. For normal opera-
tion, this input has to be either LOW or NC (No Connect).
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