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IDT54FCT810CTLB

Description
Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CQCC20, LCC-20
Categorylogic    logic   
File Size107KB,6 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT54FCT810CTLB Overview

Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, CQCC20, LCC-20

IDT54FCT810CTLB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQLCC
package instructionLCC-20
Contacts20
Reach Compliance Codenot_compliant
Is SamacsysN
Other featuresONE BANK WITH ALL TRUE OUTPUTS & OTHER WITH ALL INVERTED OUTPUTS; MAX PART TO PART SKEW = 1.2NS
seriesFCT
Input adjustmentSCHMITT TRIGGER
JESD-30 codeS-CQCC-N20
JESD-609 codee0
length8.89 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
MaximumI(ol)0.032 A
Number of functions1
Number of inverted outputs5
Number of terminals20
Actual output times5
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Encapsulate equivalent codeLCC20,.35SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Prop。Delay @ Nom-Sup4.6 ns
propagation delay (tpd)4.6 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)1 ns
Filter level38535Q/M;38534H;883B
Maximum seat height2.54 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width8.89 mm
Base Number Matches1
FAST CMOS
BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
IDT54/74FCT810BT/CT
FEATURES:
0.5 MICRON CMOS technology
Guaranteed low skew < 600ps (max.)
Very low duty cycle distortion < 700ps (max.)
Low CMOS power levels
TTL compatible inputs and outputs
TTL level output voltage swings
High drive: –32mA I
OH
, 48mA I
OL
Two independent output banks with 3-state control
– One 1:5 Inverting bank
– One 1:5 Non-Inverting bank
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ non-
inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. The part has multiple grounds, minimizing the effects of
ground inductance.
FUNCTIONAL BLOCK DIAGRAMS
PIN CONFIGURATIONS
V
CC
1
2
3
4
5
6
7
8
9
10
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
20
19
18
17
16
15
14
13
12
11
V
CC
OB
1
OB
2
OB
3
GND
OB
4
OB
5
GND
OE
B
IN
B
3103 drw 02
OE
A
5
IN
A
OA
1
-OA
5
OA
1
OA
2
OA
3
GND
OE
B
5
IN
B
OB
1
-OB
5
3103 drw 01
OA
4
OA
5
GND
OE
A
IN
A
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
OA
2
OA
1
INDEX
3
OA
3
GND
OA
4
OA
5
GND
4
5
6
7
8
2
1
20 19
18
17
OB
2
OB
3
GND
OB
4
OB
5
L20-2
OB
1
16
15
14
9 10 11 12 13
OE
A
V
CC
IN
B
OE
B
IN
A
V
CC
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC
TOP VIEW
GND
3103 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
OCTOBER 1995
DSC-4646/3
9.4
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