MCP3202
2.7V Dual Channel 12-Bit A/D Converter
with SPI Serial Interface
Features
•
•
•
•
•
•
•
•
•
•
•
12-bit resolution
±1 LSB max DNL
±1 LSB max INL (MCP3202-B)
±2 LSB max INL (MCP3202-C)
Analog inputs programmable as single-ended or
pseudo-differential pairs
On-chip sample and hold
SPI serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V-5.5V
100 ksps max. sampling rate at V
DD
= 5V
50 ksps max. sampling rate at V
DD
= 2.7V
Low power CMOS technology
- 500 nA typical standby current, 5
μA
max.
- 550 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
8-pin MSOP, PDIP, SOIC and TSSOP packages
Package Types
PDIP, MSOP, SOIC, TSSOP
CS/SHDN
CH0
CH1
V
SS
1
2
3
4
8
7
6
5
V
DD
/V
REF
CLK
D
OUT
D
IN
Functional Block Diagram
V
DD
V
SS
MCP3202
•
•
CH0
CH1
Input
Channel
Mux
DAC
Comparator
Applications
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
Sample
and
Hold
12-Bit SAR
Control Logic
Shift
Register
Description
The Microchip Technology Inc. MCP3202 is a succes-
sive approximation 12-bit Analog-to-Digital (A/D)
Converter with on-board sample and hold circuitry. The
MCP3202 is programmable to provide a single pseudo-
differential input pair or dual single-ended inputs. Differ-
ential Nonlinearity (DNL) is specified at ±1 LSB, and
Integral Nonlinearity (INL) is offered in ±1 LSB
(MCP3202-B) and ±2 LSB (MCP3202-C) versions.
Communication with the device is done using a simple
serial interface compatible with the SPI protocol. The
device is capable of conversion rates of up to 100 ksps
at 5V and 50 ksps at 2.7V. The MCP3202 device oper-
ates over a broad voltage range (2.7V-5.5V). Low-
current design permits operation with typical standby
and active currents of only 500 nA and 375
μA,
respec-
tively. The MCP3202 is offered in 8-pin MSOP, PDIP,
TSSOP and 150 mil SOIC packages.
CS/SHDN
D
IN
CLK
D
OUT
©
2006 Microchip Technology Inc.
DS21034D-page 1
MCP3202
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
Name
V
DD
/V
REF
Function
+2.7V to 5.5V Power Supply and
Reference Voltage Input
Channel 0 Analog Input
Channel 1 Analog Input
Serial Clock
Serial Data In
Serial Data Out
Chip Select/Shutdown Input
V
DD
.........................................................................7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
DD
+0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
ESD protection on all pins (HBM).........................
>
4 kV
*Notice:
Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
CH0
CH1
CLK
D
IN
D
OUT
CS/SHDN
ELECTRICAL CHARACTERISTICS
All parameters apply at V
DD
= 5.5V, V
SS
= 0V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100 ksps and f
CLK
= 18*f
SAMPLE
unless otherwise noted.
Parameter
Conversion Rate:
Conversion Time
Analog Input Sample Time
Sym
t
CONV
t
SAMPLE
Min.
—
Typ.
—
1.5
Max.
12
Units
clock
cycles
clock
cycles
ksps
ksps
bits
LSB
LSB
LSB
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
Conditions
Throughput Rate
DC Accuracy:
Resolution
Integral Nonlinearity
Differential Nonlinearity
f
SAMPLE
—
—
—
—
12
±0.75
±1
±0.5
100
50
INL
DNL
—
—
—
±1
±2
±1
MCP3202-B
MCP3202-C
No missing codes over
temperature
Offset Error
—
±1.25
±3
LSB
Gain Error
—
±1.25
±5
LSB
Dynamic Performance:
Total Harmonic Distortion
THD
—
-82
—
dB
V
IN
= 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion
SINAD
—
72
—
dB
V
IN
= 0.1V to 4.9V@1 kHz
(SINAD)
Spurious Free Dynamic Range
SFDR
—
86
—
dB
V
IN
= 0.1V to 4.9V@1 kHz
Analog Inputs:
—
V
DD
V
Input Voltage Range for CH0 or
V
SS
CH1 in Single-Ended Mode
See Sections 3.1 and 4.1
Input Voltage Range for IN+ in
IN+
IN-
—
V
DD
+IN-
Pseudo-Differential Mode
—
V
SS
+100
mV
See Sections 3.1 and 4.1
Input Voltage Range for IN- in
IN-
V
SS
-100
Pseudo-Differential Mode
Leakage Current
—
.001
±1
μA
Switch Resistance
R
SS
—
1k
—
Ω
See Figure 4-1
Note 1:
This parameter is established by characterization and not 100% tested.
2:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
DS21034D-page 2
©
2006 Microchip Technology Inc.
MCP3202
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at V
DD
= 5.5V, V
SS
= 0V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100 ksps and f
CLK
= 18*f
SAMPLE
unless otherwise noted.
Parameter
Sample Capacitor
Digital Input/Output:
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
(All Inputs/Outputs)
Timing Parameters:
Clock Frequency
Clock High Time
Clock Low Time
CS Fall To First Rising CLK
Edge
Data Input Setup Time
Data Input Hold Time
CLK Fall To Output Data Valid
CLK Fall To Output Enable
CS Rise To Output Disable
CS Disable Time
D
OUT
Rise Time
D
OUT
Fall Time
Sym
C
SAMPLE
Min.
—
Typ.
20
Max.
—
Units
pF
Conditions
See Figure 4-1
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
C
IN
, C
OUT
Straight Binary
0.7 V
DD
—
—
—
—
0.3 V
DD
4.1
—
—
—
—
0.4
-10
—
10
-10
—
10
—
—
10
V
V
V
V
µA
µA
pF
I
OH
= -1 mA, V
DD
= 4.5V
I
OL
= 1 mA, V
DD
= 4.5V
V
IN
= V
SS
or V
DD
V
OUT
= V
SS
or V
DD
V
DD
= 5.0V (Note
1)
T
AMB
= 25°C, f = 1 MHz
V
DD
= 5V (Note
2)
V
DD
= 2.7V (Note
2)
f
CLK
t
HI
t
LO
t
SUCS
t
SU
t
HD
t
DO
t
EN
t
DIS
t
CSH
t
R
t
F
—
250
250
100
—
—
—
—
—
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.8
0.9
—
—
—
50
50
200
200
100
—
100
100
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
Note 1
See Test Circuits, Figure 1-2
Note 1
See Test Circuits, Figure 1-2
Note 1
Power Requirements:
2.7
—
5.5
V
Operating Voltage
V
DD
Operating Current
I
DD
—
375
550
µA
V
DD
= 5.0V, D
OUT
unloaded
—
0.5
5
µA
CS = V
DD
= 5.0V
Standby Current
I
DDS
Temperature Ranges:
Specified Temperature Range
T
A
-40
—
+85
°C
-40
—
+85
°C
Operating Temperature Range
T
A
Storage Temperature Range
T
A
-65
—
+150
°C
Thermal Package Resistance:
Thermal Resistance, 8L-PDIP
θ
JA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θ
JA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θ
JA
—
206
—
°C/W
θ
JA
—
—
°C/W
Thermal Resistance, 8L-TSSOP
Note 1:
This parameter is established by characterization and not 100% tested.
2:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
©
2006 Microchip Technology Inc.
DS21034D-page 3
MCP3202
t
CSH
CS
t
SUCS
t
HI
CLK
t
SU
D
IN
t
HD
t
LO
MSB IN
t
EN
t
DO
NULL BIT
MSB OUT
t
R
t
F
LSB
t
DIS
D
OUT
FIGURE 1-1:
Serial Timing.
Load circuit for t
DIS
and t
EN
Test Point
V
DD
3 kΩ
Test Point
D
OUT
C
L
= 100 pF
100 pF
V
SS
3 kΩ
V
DD
/2
t
DIS
Waveform 2
t
EN
Waveform
t
DIS
Waveform 1
Load circuit for t
R
, t
F
, t
DO
1.4V
D
OUT
Voltage Waveforms for t
R
, t
F
D
OUT
t
R
t
F
CLK
D
OUT
V
OH
V
OL
Voltage Waveforms for t
EN
CS
1
2
3
4
B11
t
EN
Voltage Waveforms for t
DO
CLK
t
DO
D
OUT
Voltage Waveforms for t
DIS
CS
D
OUT
Waveform 1*
T
DIS
D
OUT
Waveform 2†
10%
V
IH
90%
*
Waveform 1 is for an output with internal conditions such that
the output is high, unless disabled by the output control.
† Waveform 2 is for an output with internal conditions such that
the output is low, unless disabled by the output control.
FIGURE 1-2:
Test Circuits.
DS21034D-page 4
©
2006 Microchip Technology Inc.
MCP3202
2.0
Note:
TYPICAL PERFORMANCE CHARACTERISTICS
The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, V
DD
= 5V, V
SS
= 0V, f
SAMPLE
=
100 ksps, f
CLK
= 18* f
SAMPLE
,T
A
= 25°C
1.0
0.8
0.6
0.4
Positive INL
2.0
1.5
1.0
V
DD
= 2.7V
Positive INL
0.5
0.0
-0.5
Negative INL
-1.0
-1.5
-2.0
0
20
40
60
80
100
INL (LSB)
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25
50
75
100
125
150
Negative INL
Sample Rate (ksps)
INL (LSB)
Sample Rate (ksps)
FIGURE 2-1:
Rate.
Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4:
Integral Nonlinearity (INL) vs. Sample
Rate (V
DD
= 2.7V).
1.0
0.8
0.6
0.4
Positive INL
F
SAMPLE
= 100 ksps
1.0
0.8
0.6
0.4
Positive INL
F
SAMPLE
= 50 ksps
INL (LSB)
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
3.0
3.5
4.0
4.5
5.0
Negative INL
INL (LSB)
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
2.5
3.0
3.5
4.0
4.5
5.0
Negative INL
V
DD
(V)
V
DD
(V)
FIGURE 2-2:
Integral Nonlinearity (INL) vs. V
DD
.
FIGURE 2-5:
Integral Nonlinearity (INL) vs. V
DD
.
1.0
0.8
0.6
0.4
1.0
0.8
0.6
0.4
V
DD
= 2.7V
F
SAMPLE
= 50 ksps
INL (LSB)
INL (LSB)
0
512
1024
1536 2048
2560 3072
3584 4096
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024
1536 2048
2560 3072
3584 4096
Digital Code
Digital Code
FIGURE 2-3:
Integral Nonlinearity (INL) vs. Code
(Representative Part).
FIGURE 2-6:
Integral Nonlinearity (INL) vs. Code
(Representative Part, V
DD
= 2.7V).
©
2006 Microchip Technology Inc.
DS21034D-page 5
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