MCP3201
2.7V 12-Bit A/D Converter with SPI
™
Serial Interface
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
12-bit resolution
±1 LSB max DNL
±1 LSB max INL (MCP3201-B)
±2 LSB max INL (MCP3201-C)
On-chip sample and hold
SPI
™
serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at V
DD
= 5V
50ksps max. sampling rate at V
DD
= 2.7V
Low power CMOS technology
500 nA typical standby current, 2 µA max.
400 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
8-pin MSOP, PDIP, SOIC and TSSOP packages
Package Types
MSOP, PDIP, SOIC, TSSOP
V
REF
IN+
IN–
V
SS
1
MCP3201
V
REF
8
7
6
5
V
DD
CLK
D
OUT
CS/SHDN
2
3
4
Functional Block Diagram
V
DD
V
SS
Applications
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
DAC
Comparator
IN+
IN-
Sample
and
Hold
Control Logic
12-Bit SAR
Description
The Microchip Technology Inc. MCP3201 is a succes-
sive approximation 12-bit Analog-to-Digital (A/D) Con-
verter with on-board sample and hold circuitry. The
device provides a single pseudo-differential input. Dif-
ferential Nonlinearity (DNL) is specified at ±1 LSB, and
Integral Nonlinearity (INL) is offered in ±1 LSB
(MCP3201-B) and ±2 LSB (MCP3201-C) versions.
Communication with the device is done using a simple
serial interface compatible with the SPI protocol. The
device is capable of sample rates of up to 100 ksps at
a clock rate of 1.6 MHz. The MCP3201 operates over
a broad voltage range (2.7V - 5.5V). Low current
design permits operation with typical standby and
active currents of only 500 nA and 300 µA, respec-
tively. The device is offered in 8-pin MSOP, PDIP,
TSSOP and 150 mil SOIC packages.
Shift
Register
CS/SHDN
CLK
D
OUT
©
2007 Microchip Technology Inc.
DS21290D-page 1
MCP3201
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
Name
Function
V
DD
V
SS
IN+
IN-
CLK
D
OUT
CS/SHDN
V
REF
+2.7V to 5.5V Power Supply
Ground
Positive Analog Input
Negative Analog Input
Serial Clock
Serial Data Out
Chip Select/Shutdown Input
Reference Voltage Input
V
DD
.........................................................................7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
DD
+0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
ESD protection on all pins (HBM)....................... > 4 kV
*Notice:
Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100 ksps, and f
CLK
= 16*f
SAMPLE
unless otherwise noted.
Parameter
Conversion Rate:
Conversion Time
Analog Input Sample Time
Throughput Rate
DC Accuracy:
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Dynamic Performance:
Total Harmonic Distortion
Signal to
(SINAD)
Noise
and
Distortion
THD
SINAD
SFDR
—
—
—
0.25
—
—
-82
72
86
—
100
.001
—
—
—
V
DD
150
3
dB
dB
dB
V
µA
µA
V
IN
= 0.1V to 4.9V@1 kHz
V
IN
= 0.1V to 4.9V@1 kHz
V
IN
= 0.1V to 4.9V@1 kHz
Note 2
CS = V
DD
= 5V
INL
DNL
—
—
—
—
—
12
±0.75
±1
±0.5
±1.25
±1.25
±1
±2
±1
±3
±5
bits
LSB
LSB
LSB
LSB
LSB
MCP3201-B
MCP3201-C
No missing codes over
temperature
t
CONV
t
SAMPLE
f
SAMPLE
—
—
—
1.5
—
100
50
12
clock
cycles
clock
cycles
ksps
ksps
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
Sym
Min
Typ
Max
Units
Conditions
Spurious Free Dynamic Range
Reference Input:
Voltage Range
Current Drain
Analog Inputs:
Input Voltage Range (IN+)
Input Voltage Range (IN-)
Leakage Current
Switch Resistance
Note 1:
2:
3:
IN+
IN-
IN-
V
SS
-100
—
—
V
REF
+IN-
V
SS
+100
V
mV
µA
W
See Figure 4-1
0.001
1K
±1
—
R
SS
—
This parameter is established by characterization and not 100% tested.
See graph that relates linearity performance to V
REF
level.
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 for more information.
DS21290D-page 2
©
2007 Microchip Technology Inc.
MCP3201
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100 ksps, and f
CLK
= 16*f
SAMPLE
unless otherwise noted.
Parameter
Sample Capacitor
Digital Input/Output:
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
(all inputs/outputs)
Timing Parameters:
Clock Frequency
Clock High Time
Clock Low Time
CS Fall To First Rising CLK Edge
CLK Fall To Output Data Valid
CLK Fall To Output Enable
CS Rise To Output Disable
CS Disable Time
D
OUT
Rise Time
D
OUT
Fall Time
Power Requirements:
Operating Voltage
Operating Current
Standby Current
Temperature Ranges:
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistance:
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-TSSOP
Note 1:
2:
3:
q
JA
q
JA
q
JA
q
JA
—
—
—
—
85
163
206
124
—
—
—
—
°C/W
°C/W
°C/W
°C/W
T
A
T
A
T
A
-40
-40
-65
—
—
—
+85
+85
+150
°C
°C
°C
V
DD
I
DD
I
DDS
2.7
—
—
—
—
300
210
0.5
5.5
400
—
2
V
µA
µA
µA
V
DD
= 5.0V, D
OUT
unloaded
V
DD
= 2.7V, D
OUT
unloaded
CS = V
DD
= 5.0V
f
CLK
t
HI
t
LO
t
SUCS
t
DO
t
EN
t
DIS
t
CSH
t
R
t
F
—
—
312
312
100
—
—
—
625
—
—
—
—
—
—
—
—
—
—
—
—
—
1.6
0.8
—
—
—
200
200
100
—
100
100
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Test Circuits, Figure 1-2
(Note 1)
See Test Circuits, Figure 1-2
(Note 1)
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
(Note 1)
V
DD
= 5V
(Note 3)
V
DD
= 2.7V
(Note 3)
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
C
IN
, C
OUT
0.7 V
DD
—
4.1
—
-10
-10
—
Straight Binary
—
—
—
—
—
—
—
—
0.3 V
DD
—
0.4
10
10
10
V
V
V
V
µA
µA
pF
I
OH
= -1 mA, V
DD
= 4.5V
I
OL
= 1 mA, V
DD
= 4.5V
V
IN
= V
SS
or V
DD
V
OUT
= V
SS
or V
DD
V
DD
= 5.0V
(Note 1)
T
AMB
= 25°C, f = 1 MHz
Sym
C
SAMPLE
Min
—
Typ
20
Max
—
Units
pF
Conditions
See Figure 4-1
This parameter is established by characterization and not 100% tested.
See graph that relates linearity performance to V
REF
level.
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 for more information.
©
2007 Microchip Technology Inc.
DS21290D-page 3
MCP3201
t
CSH
CS
t
SUCS
t
HI
CLK
t
EN
D
OUT
FIGURE 1-1:
HI-Z
t
DO
t
R
MSB OUT
t
DIS
t
F
LSB
HI-Z
t
LO
NULL BIT
Serial Timing.
Load circuit for t
DIS
and t
EN
Test Point
V
DD
3 kΩ
Test Point
D
OUT
C
L
= 30 pF
30 pF
V
SS
3 kΩ
t
DIS
Waveform 2
t
EN
Waveform
t
DIS
Waveform 1
Load circuit for t
R
, t
F
, t
DO
1.4V
D
OUT
V
DD
/2
Voltage Waveforms for t
R
, t
F
V
OH
V
OL
t
R
t
F
CLK
D
OUT
Voltage Waveforms for t
EN
D
OUT
CS
1
2
3
4
B9
t
EN
Voltage Waveforms for t
DO
CS
CLK
t
DO
D
OUT
Voltage Waveforms for t
DIS
V
IH
90%
t
DIS
D
OUT
Waveform 2†
10%
D
OUT
Waveform 1*
* Waveform 1 is for an output with internal condi-
tions such that the output is high, unless disabled
by the output control.
† Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
DS21290D-page 4
©
2007 Microchip Technology Inc.
MCP3201
2.0
Note:
TYPICAL PERFORMANCE CHARACTERISTICS
The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100 ksps, f
CLK
= 16*f
SAMPLE
,T
A
= 25°C
1.0
0.8
0.6
0.4
Positive INL
2.0
1.5
1.0
V
DD
= V
REF
= 2.7V
Positive INL
INL (LSB)
INL (LSB)
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25
50
75
100
125
150
Negative INL
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
20
40
60
80
100
Negative INL
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1:
Rate.
Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4:
Integral Nonlinearity (INL) vs. Sample
Rate (V
DD
= 2.7V).
2.0
1.5
1.0
Positive INL
2.0
1.5
1.0
Positive INL
V
DD
= 2.7V
F
SAMPLE
= 50 ksps
INL (LSB)
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
1
INL (LSB)
0.5
0.0
-0.5
-1.0
-1.5
-2.0
Negative INL
Negative INL
2
3
4
5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
REF
(V)
V
REF
(V)
FIGURE 2-2:
Integral Nonlinearity (INL) vs. V
REF
.
FIGURE 2-5:
(V
DD
= 2.7V).
Integral Nonlinearity (INL) vs. V
REF
1.0
0.8
0.6
0.4
1.0
0.8
0.6
0.4
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50 ksps
INL (LSB)
INL (LSB)
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024
1536 2048
2560 3072
3584 4096
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024 1536
2048 2560 3072
3584 4096
Digital Code
Digital Code
FIGURE 2-3:
Integral Nonlinearity (INL) vs. Code
(Representative Part).
FIGURE 2-6:
Integral Nonlinearity (INL) vs. Code
(Representative Part, V
DD
= 2.7V).
©
2007 Microchip Technology Inc.
DS21290D-page 5
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