MCP23008/MCP23S08
8-Bit I/O Expander with Serial Interface
Features
• 8-Bit Remote Bidirectional I/O Port
- I/O pins default to input
• High-Speed I
2
C Interface (MCP23008)
- 100 kHz
- 400 kHz
- 1.7 MHz
• High-Speed SPI Interface (MCP23S08)
- 10 MHz
• Hardware Address Pins
- Three for the MCP23008 to allow up to eight
devices on the bus
- Two for the MCP23S08 to allow up to four
devices using the same Chip Select
• Configurable Interrupt Output Pin
- Configurable as active-high, active-low or
open-drain
• Configurable Interrupt Source
- Interrupt-on-change from configured defaults
or pin change
• Polarity Inversion Register to Configure the
Polarity of the Input Port Data
• External Reset Input
• Low Standby Current: 1 µA (max.)
• Operating Voltage:
- 1.8V to 5.5V at -40°C to +85°C
I
2
C at 100 kHz
SPI at 5 MHz
- 2.7V to 5.5V at -40°C to +85°C
I
2
C at 400 kHz
SPI at 10 MHz
- 4.5V to 5.5V at -40°C to +125°C
I
2
C at 1.7 kHz
SPI at 10 MHz
Packages
•
•
•
•
18-pin PDIP (300 mil)
18-pin SOIC (300 mil)
20-pin SSOP
20-pin QFN
Block Diagram
MCP23S08
SCK
SI
SO
MCP23008
SCL
SDA
MCP23S08
A1:A0
A2:A0
RESET
INT
Interrupt
Logic
8
V
DD
V
SS
POR
Configuration/
Control
Registers
3
Serial
Interface
Decode
Control
Serializer/
Deserializer
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
8
GPIO
2004-2019 Microchip Technology Inc.
DS20001919F-page 1
MCP23008/MCP23S08
Package Types
MCP23008
PDIP/SOIC
SCL
SDA
A2
A1
A0
RESET
NC
INT
V
SS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
SCL
SDA
A2
A1
A0
RESET
NC
INT
V
SS
N/C
1
2
3
4
5
6
7
8
9
10
SSOP
20
19
18
17
16
15
14
13
12
11
V
DD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
N/C
MCP23008
QFN
SDA
GP7
SCL
V
DD
V
SS
20
19
18
17
16
A2
A1
A0
RESET
NC
1
2
3
4
5
10
6
7
8
9
MCP23008
15
14
13
12
11
GP6
GP5
GP4
GP3
GP2
GP0
2004-2019 Microchip Technology Inc.
GP1
N/C
N/C
INT
MCP23008
DS20001919F-page 2
MCP23008/MCP23S08
Package Types: (Continued)
PDIP/SOIC
SCK
SI
SO
A1
A0
RESET
CS
INT
V
SS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
MCP23S08
SCK
SI
SO
A1
A0
RESET
CS
INT
V
SS
N/C
1
2
3
4
5
6
7
8
9
10
SSOP
20
19
18
17
16
15
14
13
12
11
V
DD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
N/C
MCP23S08
QFN
SCK
GP7
V
DD
V
SS
SI
20
19
18
17
16
SO
A1
A0
RESET
CS
1
2
3
4
5
10
6
7
8
9
MCP23S08
15
14
13
12
11
GP6
GP5
GP4
GP3
GP2
GP0
2004-2019 Microchip Technology Inc.
GP1
N/C
N/C
INT
MCP23S08
DS20001919F-page 3
MCP23008/MCP23S08
1.0
DEVICE OVERVIEW
The MCP23X08 device provides 8-bit, general
purpose, parallel I/O expansion for I
2
C bus or SPI
applications. The two devices differ in the number of
hardware address pins and the serial interface:
• MCP23008 – I
2
C interface; three address pins
• MCP23S08 – SPI interface; two address pins
The MCP23X08 consists of multiple 8-bit Configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O Configuration bits. The data
for each input or output is kept in the corresponding
Input or Output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion
register. All registers can be read by the system master.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1.
When any input state differs from its
corresponding Input Port register state, this is
used to indicate to the system master that an
input state has changed.
When an input state differs from a preconfigured
register value (DEFVAL register).
2.
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
1.1
Pin Descriptions
PINOUT DESCRIPTION
QFN
19
20
1
SSOP
1
2
3
Pin
Type
I
I/O
I/O
Serial clock input.
Serial data I/O (MCP23008)/Serial data input (MCP23S08).
Hardware address input (MCP23008)/
Serial data output (MCP23S08).
A2 must be biased externally.
Hardware address input. Must be biased externally.
Hardware address input. Must be biased externally.
External Reset input. Must be biased externally.
No connect (MCP23008)/External Chip Select input (MCP23S08).
Interrupt output. Can be configured for active-high, active-low or
open-drain.
Ground.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
Power.
—
Function
TABLE 1-1:
Pin
Name
SCL/SCK
SDA/SI
A2/SO
PDIP/
SOIC
1
2
3
A1
A0
RESET
NC/CS
INT
V
SS
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
V
DD
N/C
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
—
2
3
4
5
7
17
9
10
11
12
13
14
15
16
18
6, 8
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
10, 11
I
I
I
I
O
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
—
2004-2019 Microchip Technology Inc.
DS20001919F-page 4
MCP23008/MCP23S08
1.2
Power-on Reset (POR)
1.3.2
1.3.2.1
I
2
C INTERFACE
I
2
C Write Operation
The on-chip POR circuit holds the device in Reset until
V
DD
has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from Reset).
The maximum V
DD
rise time is specified in
Section 2.0, Electrical Characteristics.
When the device exits the POR condition (releases
Reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
The I
2
C Write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1.
This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23008. The operation is ended with a STOP
or RESTART condition being generated by the master.
Data is written to the MCP23008 after every byte
transfer. If a STOP or RESTART condition is
generated during a data transfer, the data will not be
written to the MCP23008.
Byte writes and sequential writes are both supported
by the MCP23008. The MCP23008 increments its
address counter after each ACK during the data
transfer.
1.3
Serial Interface
This block handles the functionality of the I
2
C
(MCP23008) or SPI (MCP23S08) interface protocol.
The MCP23X08 contains eleven registers that can be
addressed through the serial interface block (Table
1-2):
TABLE 1-2:
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
REGISTER ADDRESSES
Access to:
IODIR
IPOL
GPINTEN
DEFVAL
INTCON
IOCON
GPPU
INTF
INTCAP (Read-only)
GPIO
OLAT
1.3.2.2
I
2
C Read Operation
The I
2
C Read operation includes the control byte
sequence, as shown in the bottom of
Figure 1-1.
This
sequence is followed by another control byte (includ-
ing the START condition and ACK) with the R/W bit
equal to a logic ‘1’ (R/W =
1).
The MCP23008 then
transmits the data contained in the addressed register.
The sequence is ended with the master generating a
STOP or RESTART condition.
1.3.2.3
I
2
C Sequential Write/Read
1.3.1
SEQUENTIAL OPERATION BIT
For sequential operations (Write or Read), instead of
transmitting a STOP or RESTART condition after the
data transfer, the master clocks the next byte pointed to
by the Address Pointer (see
Section 1.3.1 “Sequen-
tial Operation Bit”
for details regarding sequential
operation control).
The sequence ends with the master sending a STOP or
RESTART condition.
The MCP23008 Address Pointer will roll over to
address zero after reaching the last register address.
Refer to
Figure 1-1.
The Sequential Operation (SEQOP) bit (IOCON
register) controls the operation of the Address Pointer.
The Address Pointer can either be enabled (default) to
allow the Address Pointer to increment automatically
after each data transfer, or it can be disabled.
When
operating
in
Sequential
mode
(IOCON.SEQOP =
0),
the Address Pointer automati-
cally increments to the next address after each byte
is clocked.
When operating in
Byte mode
(IOCON.SEQOP =
1),
the MCP23X08 does not increment its address
counter after each byte during the data transfer. This
gives the ability to continually read the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes.
1.3.3
1.3.3.1
SPI INTERFACE
SPI Write Operation
The SPI Write operation is started by lowering CS. The
Write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
1.3.3.2
SPI Read Operation
The SPI Read operation is started by lowering CS. The
SPI Read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
2004-2019 Microchip Technology Inc.
DS20001919F-page 5
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