IDT71V432S7PF9 datasheet, PDF - EEWORLD Datasheet

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IDT71V432S7PF9: DescriptionCache SRAM, 32KX32, 7ns, CMOS, PQFP100, PLASTIC, TQFP-100; Categorystorage storage; File Size268KB，18 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V432S7PF9 Overview

Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT71V432S7PF9 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Is Samacsys	N
Maximum access time	7 ns
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	1048576 bit
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of ports	1
Number of terminals	100
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX32
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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32K x 32 CacheRAM™

3.3V Synchronous SRAM

Burst Counter

Single Cycle Deselect

Features

IDT71V432

32K x 32 memory configuration

Supports high-performance system speed:

Commercial and Industrial:

— 5ns Clock-to-Data Access (100MHz)

— 6ns Clock-to-Data Access (83MHz)

— 7ns Clock-to-Data Access (66MHz)

Single-cycle deselect functionality (Compatible with

Micron Part # MT58LC32K32D7LG-XX)

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

Power down controlled by ZZ input

Operates with a single 3.3V power supply (+10/-5%)

Packaged in a JEDEC Standard 100-pin rectangular plastic

thin quad flatpack (TQFP).

Description

The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM

organized as 32K x 32 with full support of the Pentium™ and PowerPC™

processor interfaces. The pipelined burst architecture provides cost-

effective 3-1-1-1 secondary cache performance for processors up to

100 MHz.

The IDT71V432 CacheRAM contains write, data, address, and

control registers. Internal logic allows the CacheRAM to generate a self-

timed write based upon a decision which can be left until the extreme end

of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V432 can provide four cycles of data for

a single address presented to the CacheRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses will be defined by the internal burst counter

and the

LBO

input pin.

The IDT71V432 CacheRAM utilizes IDT's high-performance, high-

volume 3.3V CMOS process, and is packaged in a JEDEC Standard

14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board

density in both desktop and notebook applications.

Pin Description Summary

–A

BWE

CLK

ADV

ADSC

ADSP

LBO

I/O

–I/O

Address Inputs

Chip Enable

Chips Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input/Output

3.3V Power

Ground

Input

I/O

Power

Ground

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

3104 tbl 01

CacheRAM is a trademark of Integrated Device Technology.

Pentium processor is a trademark of Intel Corp.

PowerPC is a trademark of International Business Machines, Inc.

AUGUST 2001

DSC-3104/05

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