SY100E167JCTR datasheet, PDF - EEWORLD Datasheet

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SY100E167JCTR: DescriptionD Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28; Categorylogic logic; File Size154KB，3 Pages; ManufacturerMicrel ( Microchip ); Websitehttps://www.microchip.com

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SY100E167JCTR Overview

D Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28

SY100E167JCTR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	QCCJ, LDCC28,.5SQ
Reach Compliance Code	not_compliant
Is Samacsys	N
Other features	SIX 2:1 MUX FOLLOWED BY REGISTER
series	100E
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.48 mm
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	1000000000 Hz
Humidity sensitivity level	1
Number of digits	1
Number of functions	6
Number of entries	2
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature
Output characteristics	OPEN-EMITTER
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240
power supply	-4.5 V
Maximum supply current (ICC)	130 mA
Prop。Delay @ Nom-Sup	0.8 ns
propagation delay (tpd)	0.8 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	11.48 mm
minfmax	1000 MHz
Base Number Matches	1

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SEMICONDUCTOR

SYNERGY

6-BIT 2:1 MUX-REGISTER

SY10E167

SY100E167

SY10E167

SY100E167

FEATURES

1000MHz min. operating frequency

Extended 100E V

range of –4.2V to –5.5V

800ps max. clock to output

Single-ended outputs

Asynchronous Master Reset

Dual clocks

DESCRIPTION

The SY10/100E167 offer six 2:1 multiplexers followed

by D flip-flops with single-ended outputs, designed for use

in new, high-performance ECL systems. The Select (SEL)

control allows one of the two data inputs to the multiplexer

to pass through. The two external clock signals (CLK

CLK

) are gated through a logical OR operation before use

as control for the six flip-flops. The selected data are

transferred to the flip-flops on the rising edge of CLK

CLK

(or both).

The multiplexer operation is controlled by the Select

(SEL) signal which selects one of the two bits of input data

at each mux to be passed through.

When a logic HIGH is applied to the Master Reset (MR)

signal, it operates asychronously to take all outputs Q to a

logic LOW.

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

ESD protection of 2000V

Fully compatible with Motorola MC10E/100E167

Available in 28-pin PLCC package

BLOCK DIAGRAM

MUX

SEL

CLK

SEL

PIN CONFIGURATION

CCO

CLK

SEL

25 24 23 22 21 20 19

10 11

CCO

TOP VIEW

PLCC

J28-1

PIN NAMES

–D

SEL

CLK

, CLK

–Q

CCO

Function

Input Data a

Input Data b

Select Input

Clock Inputs

Master Reset

Data Outputs

to Output

Rev.: C

Amendment: /1

5-127

CCO

Issue Date: February, 1998

SY100E167JCTR Related Products

	SY100E167JCTR	SY100E167JC	SY10E167JC
Description	D Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28	D Flip-Flop, 100E Series, 6-Func, Positive Edge Triggered, 1-Bit, True Output, ECL, PQCC28, PLASTIC, LCC-28	D Flip-Flop, 10E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28
Is it Rohs certified?	incompatible	incompatible	incompatible
package instruction	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ
Reach Compliance Code	not_compliant	not_compliant	not_compliant
Other features	SIX 2:1 MUX FOLLOWED BY REGISTER	SIX 2:1 MUX FOLLOWED BY REGISTER	SIX 2:1 MUX FOLLOWED BY REGISTER
series	100E	100E	10E
JESD-30 code	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e0	e0	e0
length	11.48 mm	11.48 mm	11.48 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Sup	1000000000 Hz	1000000000 Hz	1000000000 Hz
Humidity sensitivity level	1	1	1
Number of digits	1	1	1
Number of functions	6	6	6
Number of entries	2	2	2
Number of terminals	28	28	28
Maximum operating temperature	85 °C	85 °C	85 °C
Output characteristics	OPEN-EMITTER	OPEN-EMITTER	OPEN-EMITTER
Output polarity	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ	LDCC28,.5SQ	LDCC28,.5SQ
Package shape	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240	240	240
power supply	-4.5 V	-4.5 V	-5.2 V
Maximum supply current (ICC)	130 mA	130 mA	113 mA
Prop。Delay @ Nom-Sup	0.8 ns	0.8 ns	0.8 ns
propagation delay (tpd)	0.8 ns	0.8 ns	0.8 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	4.57 mm	4.57 mm
surface mount	YES	YES	YES
technology	ECL	ECL	ECL
Temperature level	OTHER	OTHER	OTHER
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	11.48 mm	11.48 mm	11.48 mm
minfmax	1000 MHz	1000 MHz	1000 MHz
Is Samacsys	N	N	-
Base Number Matches	1	1	-

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