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IDT70908L30G

Description
Dual-Port SRAM, 64KX8, 30ns, CMOS, CPGA84, PGA-84
Categorystorage    storage   
File Size179KB,14 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70908L30G Overview

Dual-Port SRAM, 64KX8, 30ns, CMOS, CPGA84, PGA-84

IDT70908L30G Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codePGA
package instructionPGA, PGA84M,11X11
Contacts84
Reach Compliance Codenot_compliant
ECCN codeEAR99
Is SamacsysN
Maximum access time30 ns
Other featuresAUTOMATIC POWER-DOWN; LOW POWER STANDBY MODE; SELF TIMED WRITE
I/O typeCOMMON
JESD-30 codeS-CPGA-P84
JESD-609 codee0
length27.94 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Number of functions1
Number of ports2
Number of terminals84
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX8
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA84M,11X11
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum standby current0.005 A
Minimum standby current4.5 V
Maximum slew rate0.285 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width27.94 mm
Base Number Matches1
HIGH-SPEED 64K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
x
x
PRELIMINARY
IDT70908S/L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 20/25/30ns (max.)
Low-power operation
– IDT70908S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT70908L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through output mode.
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
x
x
x
x
x
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 20ns clock to data out
– Self-timed write allows fast cycle time
– 25ns cycle time, 40MHz operation
Separate upper-byte and lower-byte control for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in 84-pin Pin Grid Array (PGA) and 100-pin Thin
Quad Flatpack (TQFP) packages
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
I/O
Control
I/O
Control
A
15L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3200 drw 01
JUNE 1999
1
©1999 Integrated Device Technology, Inc.
DSC 3200/8
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