TSXPC860MHVZPU50B datasheet, PDF

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TSXPC860MHVZPU50B: DescriptionRISC Microprocessor, 32-Bit, 50MHz, CMOS, PBGA357, PLASTIC, BGA-357; CategoryThe embedded processor and controller Microcontrollers and processors; File Size908KB，96 Pages; Manufacturere2v technologies

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TSXPC860MHVZPU50B Overview

RISC Microprocessor, 32-Bit, 50MHz, CMOS, PBGA357, PLASTIC, BGA-357

TSXPC860MHVZPU50B Parametric

Parameter Name	Attribute value
Parts packaging code	BGA
package instruction	,
Contacts	357
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Is Samacsys	N
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	50 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B357
low power mode	YES
Number of terminals	357
Package body material	PLASTIC/EPOXY
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
speed	50 MHz
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal location	BOTTOM
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Features

PowerPC single issue integer core.

Precise exception model.

Extensive system development support

- on-chip watchpoints and breakpoints,

- program flow tracking,

- On-chip emulation (OnCE) development interface.

High performance (Dhrystone 2.1: 52 MIPS @ 50 MHz, 3.3V, 1.3 Watts total power).

Low power (< 241 mW @25 MHz, 2.4 V internal, 3.3 V I/O-core, caches, MMUs, I/O).

MPC8XX PowerPC system interface, including a periodic interrupt timer, a bus monitor, and

real-time clocks.

Single Issue, 32-Bit Version of the Embedded PowerPC Core (fully Compatible with Book 1 of

the PowerPC Architecture Definition) with 32 X 32 – Bit Fixed Point Registers

– Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch,

without Conditional Execution

– 4 Kbyte Data Cache and 4 Kbyte Instruction Cache, Each with an MMU

– Instruction and Data Caches are two way, Set Associative, Physical Address, 4 Word Line

Burst, Least Recently Used (LRU) Replacement, Lockable On-Line Granularity

– MMUs with 32 Entry TLB, Fully associative Instruction and Data TLBs

– MMUs Support Multiple Page Sizes of 4kB, 16 kB, 256 KB, 512 KB and 8 MB ; 16 Virtual

Address Spaces and 8 Protection Groups

– Advanced On-Chip-Emulation Debug Mode

Up to 32-bit Data Bus

(Dynamic Bus Sizing for 8 and 16 bits).

32 Address Lines

Fully Static Design.

= +3.3 V± 5 % .

max

= 66 MHz (80 MHZ tbc)

TSPC860

32 BIT QUAD INTEGRATED

POWER QUICC

COMMUNICATION

CONTROLLER

PRELIMINARY

SPECIFICATION

beta SITE

Military temperature range : –55°C < T

< +125°C.

= 0.75 W typical @ 66 MHz

ATM SAR support available on TSPC860SR version

Description

The TSPC860 PowerPCt QUad Integrated Communication Controller (Power

QUICCt)

is a

versatile one-chip integrated microprocessor and peripheral combination that can be used in a

variety of controller applications. It particularly excels in communications and networking sys-

tems. The Power QUICC (pronounced ”quick”) can be described as a PowerPC-based derivative

of TS68EN360 (QUICCt).

The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory man-

agement units (MMUs) and instruction and data caches. The communications processor module

(CPM) of the TS68EN360 QUICC has been enhanced with the addition of the interprocessor-inte-

grated controller (I

C) channel. Moderate to high digital signal processing (DSP) functionality has

been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to

support any type of memory, including high performance memories and newer dynamic random

access memories (DRAMs). Overall system functionality is completed with the addition of a

PCMCIA socket controller supporting up to two sockets and a real-time clock.

PBGA 357

ZP suffix

Screening / Quality

This product will be manufactured in full compliance with :

Or according to ATMEL-Grenoble standard.

August 2000

1/96

SUMMARY

A. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . 3

1. MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. PIN ASSIGNEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1. Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.8. Ethernet Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.9. I2C AC Electrical Specifications SCL < 100 KHz . . . . . . . . . . . . 83

5.10. SPI Master AC Electrical Specifications . . . . . . . . . . . . . . . . . . . 84

5.11. SPI Slave AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 86

5.12. I2C AC Electrical Specifications SCL < 100 KHz . . . . . . . . . . . 88

5.13. I2C AC Electrical Specifications SCL > 100 KHz . . . . . . . . . . . 89

5.6. SCC In NMSI Mode External Clock Electrical Specifications . . 75

5.7. SCC In NMSI Mode Internal Clock Electrical Specifications . . 76

3. SIGNALS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1. System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2. Active Pull up Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3. Internal Pull Up and Pull Down Resistors . . . . . . . . . . . . . . . . . . 26

3.4. Recommended Basic Pin Connections . . . . . . . . . . . . . . . . . . . . . 27

3.4.1. Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.1.1.Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4.2. JTAG and Debug Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4.3. Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4.4. Unused Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.5. Signal States during Hardware Reset . . . . . . . . . . . . . . . . . . . . . . 27

6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . . . . . . . 90

6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

B. DETAILED SPECIFICATIONS . . . . . . . . . . . . . . 29

1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . 29

3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2. Design and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.2. Lead material and finish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7. POWER CONSIDERATION . . . . . . . . . . . . . . . . . . . . . . . 90

8. LAYOUT PRACTICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

9. FUNCTIONAL UNITS DESCRIPTION . . . . . . . . . . . . . . 90

9.1. Embedded PowerPC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.2. System Interface Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.2.1. PCMCIA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.2.2. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

9.2.3. Communications Processor Module (CPM) . . . . . . . . . . . . . . . 92

9.3. Software Compatibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

9.4. TSPC860 PowerQUICC Glueless System Design . . . . . . . . . . . . 93

4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 30

4.1. General requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2. DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3. AC Electrical Specifications Control Timing . . . . . . . . . . . . . . . . 33

4.4. IEEE 1149.1 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . 60

10. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 94

11.1. Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5. CPM ELECTRICAL CHARACTERISTICS . . . . . . . . . . . 63

5.1. PIP/PIO AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 63

5.2. IDMA Controller AC Electrical Specifications . . . . . . . . . . . . . . 66

5.3. Baud Rate Generator AC Electrical Specifications . . . . . . . . . . . 69

5.4. Timer AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 70

5.5. Serial Interface AC Electrical Specifications . . . . . . . . . . . . . . . . 71

12. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . 96

2/96

TSPC860

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