BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
1M X 8 bit
GENERAL DESCRIPTION
BS62LV8007
• Vcc operation voltage : 2.7V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
The BS62LV8007 is a high performance , very low power CMOS Static
Random Access Memory organized as 1,048,576 words by 8 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.5uA at 3V/25
o
C and maximum access time of 55ns at 3.0V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable (CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
The BS62LV8007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8007 is available in 48B BGA and 44L TSOP2 packages.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV8007EC
BS62LV8007FC
BS62LV8007EI
BS62LV8007FI
OPERATING
TEMPERATURE
+0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
RANGE
2.7V ~ 3.6V
2.7V ~ 3.6V
SPEED
( ns )
55ns : 3.0~3.6V
70ns : 2.7~3.6V
( I
CCSB1
, Max )
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
PKG TYPE
Vcc=3V
Vcc=3V
55ns
70ns
55 / 70
55 / 70
5uA
10uA
30mA
31mA
TSOP2-44
24mA BGA-48-0912
TSOP2-44
25mA
BGA-48-0912
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
GND
DQ2
DQ3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5
6
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
FUNCTIONAL BLOCK DIAGRAM
BS62LV8007EC
BS62LV8007EI
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 4096
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
512
Column Decoder
18
Control
Address Input Buffer
2
3
4
A
NC
NC
OE
A0
A1
A2
CE2
B
NC
A3
A4
CE1
NC
NC
8
C
D0
NC
A5
A6
Data
Output
Buffer
8
D4
D
VSS
D1
A17
A7
D5
VCC
E
VCC
D3
D2
VCC
A16
D6
VSS
F
NC
A14
A15
NC
D7
A11A9 A8 A3 A2 A1 A0A10 A19
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
48-ball BGA top view
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
R0201-BS62LV8007
1
Revision 1.1
Jan.
2004
BSI
PIN DESCRIPTIONS
BS62LV8007
Function
These 20 address inputs select one of the 1,048,576 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
is
Name
A0-A19 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Gnd
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
Write
WE
X
X
H
H
L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
I/O OPERATION
High Z
High Z
D
OUT
D
IN
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
2.7V ~ 3.6V
2.7V ~ 3.6V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
10
12
pF
pF
1. This parameter is guaranteed and not 100% tested.
R0201-BS62LV8007
2
Revision 1.1
Jan.
2004
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(4)
I
CCSB
I
CCSB1
(5)
BS62LV8007
TEST CONDITIONS
Vcc=3V
PARAMETER
Guaranteed Input Low
Voltage
(3)
Guaranteed Input High
Voltage
(3)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
Standby Current-CMOS
MIN. TYP.
(1)
MAX.
-0.5
2.0
--
--
--
2.4
--
--
--
--
--
--
--
--
--
--
--
--
--
1.5
0.8
Vcc+0.3
1
1
0.4
--
31
25
1
10
UNITS
V
V
uA
uA
V
V
mA
mA
uA
Vcc=3V
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE1 = V
IH
or CE2 = V
IL
or
OE = V
IH
, V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE1= V
IL
, CE2= V
IH,
I
DQ
= 0mA, F = Fmax
(2)
55ns
70ns
Vcc=3V
Vcc=3V
Vcc=3V
CE1 = V
IH
or CE2= V
IL,
I
DQ
= 0mA
CE1≧Vcc-0.2V or CE2≦0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
Vcc=3V
Vcc=3V
1. Typical characteristics are at TA = 25
o
C.
2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc
_Max.
is 30mA(@55ns)/24mA(@70ns) during 0~70
o
C operation.
5.I
cc
s
B1
is 5uA at Vcc=3.0V and T
A
=70
o
C.
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
V
DR
PARAMETER
Vcc for Data Retention
TEST CONDITIONS
CE1≧ Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
MIN.
1.5
TYP.
(1)
--
MAX.
--
UNITS
V
I
CCDR
(3)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
--
0
0.8
--
(2)
2.5
--
--
uA
ns
ns
t
CDR
t
R
See Retention Waveform
T
RC
--
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. I
cc
DR
(Max.) is 1.3uA at T
A
=70
O
C.
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
V
DR
≥
1.5V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE1
≥
Vcc - 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
V
DR
≧
1.5V
Vcc
t
CDR
t
R
CE2
≦
0.2V
CE2
V
IL
V
IL
R0201-BS62LV8007
3
Revision 1.1
Jan.
2004
BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
BS62LV8007
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
CYCLE TIME : 70ns
Vcc=2.7~3.6V
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
(CE1)
(CE2)
CYCLE TIME : 55ns
Vcc=3.0~3.6V
MIN.
TYP.
MAX.
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
E1LQV
t
E2LQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
70
--
--
--
--
10
10
--
--
10
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
--
--
35
30
--
55
--
--
--
--
10
10
--
--
10
--
--
--
--
--
--
--
--
--
--
--
55
55
55
30
--
--
30
25
--
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Hold from Address Change
R0201-BS62LV8007
4
Revision 1.1
Jan.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE
)
READ CYCLE1
(1,2,4)
BS62LV8007
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE2
t
t
ACS2
ACS1
CE1
t
D
OUT
(5)
CLZ
t
(5)
CHZ
READ CYCLE3
(1,4)
ADDRESS
t
RC
t
OE
AA
t
CE2
OE
t
OH
t
t
t
t
(5)
CLZ
ACS2
CE1
OLZ
ACS1
t
t
OHZ
CHZ
(5)
(1,5)
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2 = V
IH
.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
R0201-BS62LV8007
5
Revision 1.1
Jan.
2004
Electronics Design Contest
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