P
RODUCT
S
PECIFICATIONS
®
Integrated Circuits Group
LH28F160S5T-L70A
Flash Memory
16M (2M × 8/1M × 16)
(Model No.: LHF16K55)
Spec No.: EL104104
Issue Date: April 17, 1998
SHARP
LHF16K55
l Handle this document carefully for it contains material protected by international copyright
law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.
l When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein
application areas. When using
in Paragraph (2), even for the
precautions given in Paragraph
in Paragraph (3).
are designed and manufactured for the following
the products covered herein for the equipment listed
following application -areas, be sure to observe the
(2). Never use the products for the equipment listed
*Office electronics
alnstrumentation and measuring equipment
*Machine tools
*Audiovisual equipment
*Home appliance
&ommunication
equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative
of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring &liability and
safety of the equipment and the overall system.
*Control and safety devices for airplanes, trains, automobiles,
transportation equipment
*Mainframe computers
l Traff ic control systems
*Gas leak detectors and automatic cutoff devices
*Rescue and security equipment
*Other safety devices and safety equipment, etc.
and other
(3) Do not use the products covered herein for the following equipment which demands
.
extremely high performance in terms of functionality, reliability, or accuracy.
*Aerospace equipment
@Communications equipment for trunk lines
*Control equipment for the nuclear power industry
*Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation
three Paragraphs to a sales representative of the company.
of the above
l Please direct all queries regarding the products covered herein to a sales representative
of the company.
‘.
Rev.1.8
SHARI=
LHFl6K55
1
CONTENTS
PAGE
1 INTRODUCTION
......................................................
3
3
6
7
7
7
7
7
7
8
8
8
8
11
11
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
5.3
5.4
5.5
5.6
5.7
5 DESIGN CONSIDERATIONS
PAGE
................................ .3C
5.1 Three-Line Output Control ................................ .3C
5.2 STS and Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit Configuration
Polling.. .............................................................
.3C
Power Supply Decoupling.. ................................ 3C
V,, Trace on Printed Circuit Boards.. ............... .3C
V,,, V,,, RP# Transitions.. .............................. .31
Power-Up/Down
Protection.. ............................. .31
Power Dissipation .............................................
.31
.3i
32
32
32
.3C
.34
.36
.3S
.41
43
1.l Product Overview.. ..............................................
2 PRINCIPLES OF OPERATION.. ..............................
2.1 Data Protection ...................................................
3 BUS OPERATION ....................................................
3.1 Read ...................................................................
3.2 Output Disable ....................................................
3.3
3.4
3.5
3.6
3.7
Standby ...............................................................
Deep Power-Down ..............................................
Read identifier Codes Operation.. .......................
Query Operation.. ................................................
Write ....................................................................
3 COMMAND DEFINITIONS .......................................
4.1 Read Array Command.. .....................................
4.2 Read Identifier Codes Command.. ....................
4.3 Read Status Register Command.. .....................
4.4 Clear Status Register Command.. .....................
4.5 Query Command.. .............................................
4.51 Block Status Register ..................................
4.5.2 CFI Query Identification String.. ...................
4.5.3 System interface Information .......................
4.5.4 Device Geometry Deffnition .........................
4.5.5 SCS OEM Specific Extended Query Table . .
4.6 Block Erase Command ......................................
4.7 Full Chip Erase Command.. ..............................
4.8 Word/Byte Write Command.. .............................
4.9 Multi Word/Byte Write Command.. ....................
4.10 Block Erase Suspend Command.. ...................
4.11 (Multi) Word/Byte Write Suspend Command ...
4.12 Set Block Lock-Bit Command.. ........................
4.13 Clear Block Lock-Bits Command.. ...................
4.14 STS Configuration Command .........................
6 ELECTRICAL SPECIFICATIONS..
........................
6.1 Absolute Maximum Ratings ...............................
6.2 Operating Conditions .........................................
6.2.1 Capacitance .................................................
6.2.2 AC Input/Output Test Conditions.. ...............
6.2.3 DC Characteristics.. .....................................
6.2.4 AC Characteristics - Read-&ly
Operations
6.2.5 AC Characteristics - Write Operations.. .......
6.2.6 Alternative CE#-Controlled Writes.. .............
6.2.7 Reset Operations .........................................
6.2.8 Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit
Configuration Performance.. .........................
44
7 ADDITIONAL
INFORMATION ....................... ........ .45
7.1 Ordering Information ................................ .I ........ 45
8 PACKAGE
AND PACKING
SPECIFICATION;;......4
6
Rev. 1.8
SHARI=
LHFl6K55
2
LH28F160S5T-L70A
16-MBIT (2MBx8/1 MBxl6)
Smart 5 Flash MEMORY
n
Smart 5 Technology
- 5V vcc
- 5V vpp
Common Flash Interface (CFI)
- Universal & Upgradable Interface
Scalable Command
Set (SCS)
n
n
Enhanced Data Protection Features
- Absolute Protection with Vpp=GND
- Flexible Block Locking
- Erase/Write Lockout during Power
Transitions
Extended Cycling Capability
- 100,000 Block Erase Cycles
- 3.2 Million Block Erase Cycles/Chip
Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode
Decreases ICC in Static Mode
Automated Write and Erase
- Command User Interface
- Status Register
Industry-Standard
Packa;ing
- 56-Lead TSOP
ETOXTM’ V Nonvolatile
Technology
Not designed
hardened
Flash
n
n
n
High Speed Write Performance
- 32 Bytes x 2 plane Page Buffer
- 2ys/Byte Write Transfer Rate
High Speed Read Performance
- 70ns(5V=0.25V), 80ns(5VT0.5V)
Enhanced Automated Suspend Options
- Write Suspend to Read
- Block Erase Suspend to Write
- Block Erase Suspend to Read
High-Density
Architecture
- Thirty-two
Symmetrically-Blocked
64-Kbyte
Erasable
Blocks
n
n
n
n
n
n
n
n
n
SRAM-Compatible
User-Configurable
Write Interface
x8 or x16 Operation
n
or rated as radiation
SHARP’s
LH28F160S5T-L70A
Flash memory with Smart 5 technology
is a high-density,
low-cost,
nonvolatile,
read/write
storage solution for a wide range of applications.
Its symmetrically-blocked
architecture,
flexible voltage
and extended cycling provide for highly flexible component
suitable for resident flash arrays, SlMMs and memory
cards. Its enhanced
suspend capabilities
provide for an ideal solution for code + data storage applications.
For
secure code storage applications,
such as networking,
where code is either directly executed
out of flash or
downloaded
to DRAM, the LH28F160S5T-L70A
offers three levels of protection:
absolute
protection
with V,, at
GND, selective hardware
block locking, or flexible software block locking. These alternatives
give designers
ultimate control of their code security needs.
The LH28F160SST-L70A
is conformed
to the flash Scalable Command
Set (SCS) and the Common Flash Interface
(CFI) specification
which enable universal and upgradable
interface, enable the highest system/device
data transfer
rates and minimize device and system-level
implementation
costs.
The LH28F160S5T-L70A
is manufactured
on SHARP’s 0.4pm ETOX TM* V process
standard package: the 56-Lead TSOP, ideal for
board constrained applications.
‘ETOX
is a trademark
of Intel Corporation.
technology.
It come in industry-
%\
Rev. 1.8
SHARP
LHFI 6K55
1 INTRODUCTION
This
LH28F160.%T-L70A
datasheet
contains
specifications.
Section 1 provides a flash memory
overview.
Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
execute code from any other flash memory
location.
array
1.l Product Overview
The LH28F160S5T-L70A
is a high-performance
16-
Mbit Smart
5 Flash memory
organized
as
2MBx8/1MBxl6.
The 2MB of data is arranged in
thirty-two
64-Kbyte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 5 technology provides a choice of Vcc and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 5V Voc
provides the highest read performance. V,, at 5V
eliminates the need for a separate 12V converter,
while
V,,=5V
maximizes
erase
and
write
performance.
In addition to flexible erase and
program voltages, the dedicated V,,
pin gives
complete data protection when V,, < VppLK.
Table 1. V,, and VP, Voltage Combinations
Offered by Smart 5 Technology
Vcr: Voltage
Vpp Voltage
5v
5v
Internal
and
detection
Circuitry
VW
vcc
automatically configures the device for optimized
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
nritten to the CUI initiates device automation. An
nternal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
slack erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
4 block erase operation erases one of the device’s
?4-Kbyte blocks typically within 0.34s (5V Vcc, 5V
Jpp) independent of other blocks. Each block can be
ndependently
erased 100,000 times (3.2 million
Ilock erases per device). Block erase suspend mode
1110~s system software to suspend block erase to
,ead or write data from any other block.
4 word/byte write is performed in byte increments
ypically within 9.241s (5V Vco, 5V VP,). A multi
vord/byte write has high speed write performance of
!us/byte (5V Voc, 5V V,,). (Multi) Word/byte write
cuspend mode enables the system to read data or
Individual block locking uses a combination of bits
and WP#, Thirty-two
block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) se1
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus
software
polling) and status
masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (m!&i) word/byte write
are suspended, or the device is In deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 70ns (t,vQv) over the commercial
temperature range (0% to +70X) and Vcc supply
voltage range of 4.75V-5.25V. At lower Vcc voltage,
the access time is 80ns (4.5V-5.5V).
The Automatic
Power
Savings
(APS)
feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical lCCR current is 1 mA at 5V Vcc.
When either CE,# or CE,#, and RP# pins are at Vco,
the I,, CMOS standby mode is enabled. When the
RP# pin is at GND, deep power-down
mode is
enabled which minimizes power consumption
and
provides write protection during reset. A reset time
(t,,o,)
is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tPHEL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
Rev. 1.8
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