Freescale Semiconductor
Hardware Specification
Document Number: MCF5275EC
Rev. 2, 08/2006
MCF5275 Integrated
Microprocessor Family Hardware
Specification
by: Microcontroller Division
The MCF5275 family is a highly integrated
implementation of the ColdFire
®
family of reduced
instruction set computing (RISC) microprocessors. This
document describes pertinent features and functions
characteristics of the MCF5275 family. The MCF5275
family includes the MCF5275, MCF5275L, MCF5274
and MCF5274L microprocessors. The differences
between these parts are summarized in
Table 1.
This
document is written from the perspective of the
MCF5275 and unless otherwise noted, the information
applies also to the MCF5275L, MCF5274 and
MCF5274L.
The MCF5275 family delivers a new level of
performance and integration on the popular version 2
ColdFire core with up to 159 (Dhrystone 2.1) MIPS @
166MHz. These highly integrated microprocessors build
upon the widely used peripheral mix on the popular
MCF5272 ColdFire microprocessor (10/100 Mbps
Ethernet MAC and USB device) by adding a second
10/100 Mbps Ethernet MAC (MCF5274 and MCF5275)
and hardware encryption (MCF5275L and MCF5275).
Contents
1
2
3
4
5
6
7
8
9
10
MCF5275 Family Configurations . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanicals/Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Preliminary Electrical Characteristics . . . . . . . . . . . . . . 18
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
© Freescale Semiconductor, Inc., 2006. All rights reserved.
•
Preliminary—Subject to Change Without Notice
MCF5275 Family Configurations
In addition, the MCF5275 family features an enhanced multiply accumulate unit (EMAC), large on-chip
memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory
controller.
These devices are ideal for cost-sensitive applications requiring significant control processing for file
management, connectivity, data buffering, and user interface, as well as signal processing in a variety of
key markets such as security, imaging, networking, gaming, and medical. This leading package of
integration and high performance allows fast time to market through easy code reuse and extensive third
party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com/coldfire.
1
MCF5275 Family Configurations
Table 1. MCF5275 Family Configurations
Module
ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit)
System Clock
Performance (Dhrystone 2.1 MIPS)
Instruction/Data Cache
Static RAM (SRAM)
Interrupt Controllers (INTC)
Edge Port Module (EPORT)
External Interface Module (EIM)
4-channel Direct-Memory Access (DMA)
DDR SDRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module (WDT)
4-channel Programmable Interval Timer Module (PIT)
32-bit DMA Timers
USB
QSPI
UART(s)
I
2
C
PWM
General Purpose I/O Module (GPIO)
CIM = Chip Configuration Module + Reset Controller Module
Debug BDM
JTAG - IEEE 1149.1 Test Access Port
Hardware Encryption
Package
2
x
x
x
x
1
x
x
4
x
x
3
x
4
x
x
x
x
—
2
x
x
x
x
1
x
x
4
x
x
3
x
4
x
x
x
x
x
MCF5274L
x
MCF5275L
x
MCF5274
x
MCF5275
x
up to 166 MHz
up to 159
16 Kbytes (configurable)
64 Kbytes
2
x
x
x
x
2
x
x
4
x
x
3
x
4
x
x
x
x
—
2
x
x
x
x
2
x
x
4
x
x
3
x
4
x
x
x
x
x
196 MAPBGA 196 MAPBGA 256 MAPBGA 256 MAPBGA
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Block Diagram
2
Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array
(MAPBGA) package.
Figure 1
shows a top-level block diagram of the MCF5275, the superset device.
EIM
(To/From SRAM backdoor)
CHIP
SELECTS
DDR
QSPI
I2C_SDA
I2C_SCL
Arbiter
INTC0
INTC1
EBI
TXDx
RXDx
RTSx
CTSx
(To/From PADI)
FAST ETHERNET
CONTROLLER
(FEC0)
PADI – Pin Muxing
FAST ETHERNET
CONTROLLER
(FEC1)
UART
0
UART
1
UART
2
I
2
C
QSPI
SDRAMC
DTOUTx
DTINx
FEC0
FEC1
USB
PWMx
D[31:16]
A[23:0]
R/W
CS[3:0]
TA
(To/From PADI)
(To/From
PADI)
DTIM
0
4 CH DMA
DTIM
1
DTIM
2
DTIM
3
JTAG
TAP
BDM
DREQ[1:0]
DACK[3:0]
V2 ColdFire CPU
DIV
EMAC
JTAG_EN
TRST
TCLK
TMS
TDI
MUX
JTAG_EN
TDO
TSIZ[1:0]
(To/From
PADI)
(To/From PADI)
4 CH PWM
64 Kbytes
SRAM
(8Kx16)x4
16 Kbytes
CACHE
(1Kx32)x4
PORTS
(GPIO)
CIM
TEA
BS[3:2]
Watchdog
Timer
(To/From Arbiter backdoor)
MDHA
RNGA
Cryptography
Modules
SKHA
USB 2.0
Full Speed
Edge
Port
PLL
CLKGEN
PIT0
PIT1
PIT2
PIT3
(To/From PADI) (To/From INTC)
Figure 1. MCF5275 Block Diagram
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Features
3
4
Features
Signal Descriptions
For a detailed feature list see the
MCF5275 Reference Manual
(MCF5275RM).
This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF5275 signals, consult the
MCF5275 Reference Manual
(MCF5275RM).
Table 2
lists the signals for the MCF5275 in functional group order. The “Dir” column is the direction for
the primary function of the pin. Refer to
Section 6, “Mechanicals/Pinouts,”
for package diagrams.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF5274 and MCF5275 Signal Information and Muxing
Signal Name
GPIO
Alternate1
Alternate2
Dir.
1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
Reset
RESET
RSTOUT
—
—
—
—
—
—
Clock
EXTAL
XTAL
CLKOUT
—
—
—
—
—
—
—
—
—
Mode Selection
CLKMOD[1:0]
RCON
—
—
—
—
—
—
I
I
N13, P13
P8
M11, N11
M6
I
O
O
L16
M16
T12
M14
N14
P9
I
O
N15
N14
K12
L12
External Memory Interface and Ports
A[23:21]
PADDR[7:5]
CS[6:4]
—
O
A11, B11, C11
A8, B8, C8
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate1
Alternate2 Dir.
1
MCF5274
MCF5275
256 MAPBGA
A12, B12, C12,
A13, B13, C13,
A14, B14, C14,
B15, C15, B16,
C16, D14, D15,
E14:16, F14:16
M1, N1, N2, N3,
P1, P2, R1, R2,
P3, R3, T3, N4,
P4, R4, T4, N5
M3, R5
K1
L13
T8
P7
D16
G16
L4
P6
MCF5274L
MCF5275L
196 MAPBGA
B9, D9, C9,
C10, B10, A11,
C11, B11, A12,
D11, C12, B13,
C13, D12, E11,
D13, E12, F11,
D14, E13, F13
J3, L1, K2, K3,
M1, L2, L3, L4,
K4, J4, M2, N1,
N2, M3, M4, N3
K1, L5
H4
K14
—
L6
B14
E14
H2
—
A[20:0]
—
—
—
O
D[31:16]
—
—
—
O
BS[3:2]
OE
TA
TEA
R/W
TSIZ1
TSIZ0
TS
TIP
PBS[3:2]
PBUSCTL[7]
PBUSCTL[6]
PBUSCTL[5]
PBUSCTL[4]
PBUSCTL[3]
PBUSCTL[2]
PBUSCTL[1]
PBUSCTL[0]
CAS[3:2]
—
—
DREQ1
—
DACK1
DACK0
DACK2
DREQ0
—
—
—
—
—
—
—
—
—
O
O
I
I
O
O
O
O
O
Chip Selects
CS[7:1]
PCS[7:1]
—
—
O
D10:13, E13,
F13, N7
R6
D8, A9, A10,
D10, B12, C14,
P4
N5
CS0
—
—
—
O
DDR SDRAM Controller
DDR_CLKOUT
DDR_CLKOUT
SD_CS[1:0]
SD_SRAS
SD_SCAS
SD_WE
SD_A10
SD_DQS[3:2]
SD_CKE
SD_VREF
—
—
PSDRAM[7:6]
PSDRAM[5]
PSDRAM[4]
PSDRAM[3]
—
PSDRAM[2:1]
PSDRAM[0]
—
—
—
CS[3:2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
I/O
O
I
T7
T6
M2, T5
L2
L1
K2
N6
M4, P5
L3
A15, T2
P6
P5
H3, M5
H1
G3
G4
N4
J2, P3
J1
A13, P2
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5