BLM31PG500SN1K datasheet, PDF - EEWORLD Datasheet

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BLM31PG500SN1K: DescriptionFerrite Chip, 1 Function(s), 3A, EIA STD PACKAGE SIZE 1206, 2 PIN; CategoryAnalog mixed-signal IC filter; File Size472KB，62 Pages; ManufacturerMurata; Websitehttps://www.murata.com; Environmental Compliance

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BLM31PG500SN1K Overview

Ferrite Chip, 1 Function(s), 3A, EIA STD PACKAGE SIZE 1206, 2 PIN

BLM31PG500SN1K Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	1206
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Confidence	2
Samacsys Status	Released
Samacsys PartID	4059659
Samacsys Pin Count	2
Samacsys Part Category	Filter
Samacsys Package Category	Other
Samacsys Footprint Name	BLM31_1 L=3.2 W=1.6 T=1.1
Samacsys Released Date	2019-10-10 10:28:45
Is Samacsys	N
Other features	MONOLITHIC TYPE
shell code	1206
structure	Chip Bead
Maximum DC resistance	0.025 Ω
filter type	FERRITE CHIP
maximum frequency	100 MHz
minimum frequency	100 MHz
high	1.1 mm
JESD-609 code	e3
length	3.2 mm
Material	Ferrite
Installation type	SURFACE MOUNT
Number of functions	1
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output impedance	50 OHM Ω
method of packing	TAPE
physical size	L3.2XB1.6XH1.1 (mm)/L0.126XB0.063XH0.043 (inch)
Rated current	3 A
Terminal surface	Tin (Sn)
width	1.6 mm
Base Number Matches	1

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MAX 7000

Programmable Logic

Device Family

Data Sheet

March 2001, ver. 6.1

Features...

High-performance, EEPROM-based programmable logic devices

(PLDs) based on second-generation MAX

architecture

5.0-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in

MAX 7000S devices

–

ISP circuitry compatible with IEEE Std. 1532

Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

devices

Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S

devices with 128 or more macrocells

Complete EPLD family with logic densities ranging from 600 to

5,000 usable gates (see

Tables 1

and

5-ns pin-to-pin logic delays with up to 175.4-MHz counter

frequencies (including interconnect)

PCI-compliant devices available

For information on in-system programmable 3.3-V MAX 7000A or 2.5-V

MAX 7000B devices, see the

MAX 7000A Programmable Logic Device Family

Data Sheet

or the

MAX 7000B Programmable Logic Device Family Data

Sheet.

Table 1. MAX 7000 Device Features

Feature

Usable

gates

Macrocells

Logic array

blocks

Maximum

user I/O pins

(ns)

FSU

(ns)

CO1

(ns)

CNT

(MHz)

EPM7032

600

2.5

151.5

EPM7064

1,250

2.5

151.5

EPM7096

1,800

7.5

4.5

125.0

EPM7128E

2,500

128

100

7.5

4.5

125.0

EPM7160E

3,200

160

104

100.0

EPM7192E

3,750

192

124

90.9

EPM7256E

5,000

256

164

90.9

Altera Corporation

A-DS-M7000-06.1

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