HD74AC175
Quad D-Type Flip-Flop
Description
The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements
where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-
High clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when Low.
Features
•
Edge-Triggered D-Type Inputs
•
•
•
•
Buffered Positive Edge-Triggered Clock
Asynchronous Common Reset
True and Complement Output
Outputs Source/Sink 24 mA
HD74AC175
Pin Arrangement
MR
1
Q
0
2
Q
0
3
D
0
4
D
1
5
Q
1
6
Q
1
7
GND 8
(Top view)
16 V
CC
15 Q
3
14
Q
3
13 D
3
12 D
2
11
Q
2
10 Q
2
9 CP
Logic Symbol
D
0
CP
D
1
D
2
D
3
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Pin Names
D
0
to D
3
CP
MR
Q
0
to Q
3
Q
0
to
Q
3
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
2
HD74AC175
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and
Q
outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their
individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and
Q
outputs to
follow. A Low input on the Master Reset (MR) will force all Q outputs Low and
Q
outputs High
independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
Inputs
@ t
n
,
MR
= H
Dn
L
H
H :
L :
t
n
:
t
n + 1
:
Outputs
@ t
n+1
Qn
L
H
High Voltage Level
Low Voltage Level
Bit Time before Clock Pulse
Bit Time after Clock Pulse
Qn
H
L
Logic Diagram
MR
CP D
3
D
2
D
1
D
0
D
Q
D
Q
D
Q
D
Q
CP Q
CD
CP Q
CD
CP Q
CD
CP Q
CD
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
3
HD74AC175
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Symbol
I
CC
I
CC
Max
80
8.0
Unit
µA
µA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
AC Characteristics
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
CP to Q
n
or
Q
n
Propagation delay
CP to Q
n
or
Q
n
Propagation delay
MR
to
Q
n
Propagation delay
MR
to Q
n
Note:
t
PHL
t
PLH
t
PHL
t
PLH
Symbol
f
max
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
149
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
9.5
7.0
8.5
6.0
7.5
5.5
8.5
6.0
Max
—
—
12.0
9.0
13.0
9.5
12.5
9.0
11.0
8.5
Ta = –40°C to +85°C
C
L
= 50 pF
Min
139
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
—
13.5
9.5
14.5
10.5
13.5
10.0
12.5
9.5
ns
ns
ns
ns
Unit
MHz
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
4
HD74AC175
AC Operating Requirements
Ta = +25°C
C
L
= 50 pF
Item
Set-up time, HIGH or LOW
D
n
to CP
Hold time, HIGH or LOW
D
n
to CP
CP pulse width HIGH or LOW
t
w
t
h
Symbol
t
su
V
CC
(V)*
1
Typ
3.3
5.0
3.3
5.0
3.3
5.0
MR
pulse width, LOW
Recovery time
MR
to CP
Note:
t
w
3.3
5.0
t
rec
3.3
5.0
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
2.0
1.0
0
0
2.5
2.0
2.5
2.0
–2.0
–1.0
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
4.5
3.0
1.0
1.0
4.5
3.5
4.5
3.5
0.0
0.0
4.5
3.0
1.0
1.0
4.5
3.5
5.0
3.5
0.0
0.0
ns
ns
ns
ns
Unit
ns
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
Typ
4.5
45.0
Unit
pF
pF
Condition
V
CC
= 5.5 V
V
CC
= 5.0 V
5
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