64 Megabit (4M x 16-bit), CMOS 1.8 Volt-Only Simultaneous
Read/Write, Multiplexed, Burst Mode Flash Memory
Data Sheet
(Advance Information)
S29VS/XS-R MirrorBit
®
Flash Family Cover Sheet
Notice to Readers:
This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Notice On Data Sheet Designations
for definitions.
Publication Number
S29VS_XS064R_00
Revision
07
Issue Date
August 7, 2012
Data
Sheet
(Advan ce
Infor m a tio n)
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V
IO
range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29VS/XS-R MirrorBit
®
Flash Family
S29VS_XS064R_00_07 August 7, 2012
S29VS/XS-R MirrorBit
®
Flash Family
S29VS064R, S29XS064R
64 Megabit (4M x 16-bit), CMOS 1.8 Volt-Only Simultaneous
Read/Write, Multiplexed, Burst Mode Flash Memory
Data Sheet
(Advance Information)
Distinctive Characteristics
Single 1.8 volt read, program and erase
(1.7 to 1.95 volt)
VersatileIO™ Feature
– Device generates data output voltages and tolerates data input
voltages as determined by the voltage on the V
CCQ
pin
– 1.8 V compatible I/O signals
Security Features
Dynamic Protection Bit (DYB)
– A command sector protection method to lock combinations of
individual sectors to prevent program or erase operations within that
sector
– Sectors can be locked and unlocked in-system at V
CC
level
Address and Data Interface Options
– Address and Data Multiplexed for reduced I/O count
(ADM) S29VS-R
– Address-High, Address-Low, Data Multiplexed for minimum I/O
count (AADM) S29XS-R
Hardware Sector Protection
– All sectors locked when V
PP
= V
IL
Handshaking feature
– Provides host system with minimum possible latency by monitoring
RDY
Simultaneous Read/Write operation
– Data can be continuously read from one bank while executing
erase/program functions in other bank
– Zero latency between read and write operations
Supports Common Flash Memory
Interface (CFI)
Manufactured on 65 nm MirrorBit
®
process technology
Cycling endurance: 100,000 cycles per sector typical
Data retention: 10 years typical
Data# Polling and toggle bits
– Provides a software method of detecting program and erase
operation completion
Burst length
– Continuous linear burst
– 8/16 word linear burst with wrap around
Secured Silicon Sector region
– 256 words accessible through a command sequence, 128 words for
the Factory Secured Silicon Sector and 128 words for the Customer
Secured Silicon Sector.
Erase Suspend/Resume
– Suspends an erase operation to read data from, or program data to,
a sector that is not being erased, then resumes the erase operation
Sector Architecture
– Four 8 kword sectors in upper-most address range
– One hundred twenty-seven 32 kword sectors
– Four banks
Program Suspend/Resume
– Suspends a programming operation to read data from a sector other
than the one being programmed, then resume the programming
operation
Packages
– 44-ball Very Thin FBGA
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch. Latency, ns (t
IACC)
Max. Synch. Burst Access, ns (t
BACC)
Max. Asynch. Access Time, ns (t
ACC
)
Max OE# Access Time, ns (t
OE
)
108
80
7.6
80
15
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V
CC
) Per Word
Effective Write Buffer Programming (V
PP
) Per Word
Sector Erase (8 kword Sector)
Sector Erase (32 kword Sector)
170 µs
14.1 µs
9 µs
350 ms
800 ms
Current Consumption (typical values)
Continuous Burst Read @ 108 MHz
Simultaneous Operation @ 108 MHz
Program/Erase
Standby Mode
32 mA
71 mA
30 mA
20 µA
Publication Number
S29VS_XS064R_00
Revision
07
Issue Date
August 7, 2012
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Advan ce
Infor m a tio n)
1. General Description
The S29V/XS064R are 64 Mb, 1.8 Volt-only, Simultaneous Read/Write, Burst Mode flash memory devices,
organized as 4,194,304 words of 16 bits each. These devices use a single V
CC
of 1.70 to 1.95 V to read,
program, and erase the memory array. A 9.0-volt V
PP
, may be used for faster program performance if desired.
These devices can also be programmed in standard EPROM programmers.
The devices operate within the temperature range of -25°C to +85°C, and are offered in Very Thin FBGA
packages. The devices are also available in the temperature range of -40°C to +85°C. Please refer to the
Specification Supplement with Publication Number S29VS064R_XS064R_SP for specification differences for
devices offered in the -45°C to +85°C temperature range.
1.1
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space
into four banks. The device allows a host system to program or erase in one bank, then immediately and
simultaneously read from another bank, with zero latency. This releases the system from waiting for the
completion of program or erase operations.
The VersatileIO™ (V
IO
) control allows the host system to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the
V
CCQ
pin.
The devices use Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to
control asynchronous read and write operations. For burst operations, the devices additionally require Ready
(RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to
microprocessors/microcontrollers for high performance read operations.
The devices offer complete compatibility with the
JEDEC 42.4 single-power-supply flash command set
standard.
Commands are written to the command register using standard microprocessor write timings.
Reading data out of the device are similar to reading from other flash or EPROM devices.
The host system can detect whether a program or erase operation is complete by using the device
status bit
DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The devices are fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The devices also offers another type of data protection at the sector level. When
V
PP
is at V
IL
, all sectors are locked.
The devices offer two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both modes.
Device programming occurs by executing the program command sequence. This initiates the
Embedded
Program
algorithm - an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Additionally,
Write Buffer Programming
is available on this family of devices. This
feature provides superior programming performance by grouping locations being programmed.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm - an internal algorithm that automatically preprograms the array (if it is not already fully
programmed) before executing the erase operation. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The
Program Suspend/Program Resume
feature enables the user to put program on hold to read data from
any sector that is not selected for programming. If a read is needed from the Dynamic Protection area, or the
CFI area, after an program suspend, then the user must use the proper command sequence to enter and exit
this region. The program suspend/resume functionality is also available when programming in erase suspend
(1 level depth only).
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If
a read is needed from the Dynamic Protection area, or the CFI area, after an erase suspend, then the user
must use the proper command sequence to enter and exit this region.
4
S29VS/XS-R MirrorBit
®
Flash Family
S29VS_XS064R_00_07 August 7, 2012
D at a
S hee t
(Adva nce
In for m ation)
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read boot-up firmware from the flash memory device.
The host system can detect whether a memory array program or erase operation is complete by using the
device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase
start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been
completed, the device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors.
The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The device also offers another type of data protection at the sector level.
When the V
PP
pin = V
IL
, the entire flash memory array is protected.
Spansion Inc. flash technology combines years of flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector. The data is programmed using hot electron injection.
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