SYNCHRONOUS PRESETTABLE
BINARY COUNTER
The MC74F161A and MC74F163A are high-speed synchronous modu-
lo-16 binary counters. They are synchronously presettable for application in
programmable dividers and have two types of Count Enable inputs plus a Ter-
minal Count output for versatility in forming synchronous multistage counters.
The MC74F161A has an asynchronous Master Reset input that overrides all
other inputs and forces the outputs LOW. The MC74F163A has a Synchro-
nous Reset input that overrides counting and parallel loading and allows the
outputs to be simultaneously reset on the rising edge of the clock.
•
Synchronous Counting and Loading
•
High-Speed Synchronous Expansion
•
Typical Count Frequency of 120 MHz
CONNECTION DIAGRAM
16
MC74F161A
MC74F163A
SYNCHRONOUS PRESETTABLE
BINARY COUNTER
FAST™ SHOTTKY TTL
J SUFFIX
CERAMIC
CASE 620-09
1
VCC
16
TC
15
Q0
14
Q1
13
Q2
12
Q3
11
CET
10
PE
9
16
1
N SUFFIX
PLASTIC
CASE 648-08
1
*R
2
CP
3
P0
4
P1
5
P2
6
P3
7
CEP
8
GND
16
1
*MR for MC74F161A
*SR for MC74F163A
D SUFFIX
SOIC
CASE 751B-03
FUNCTION TABLE
SR
L
H
H
H
H
PE
X
L
H
H
H
CET
X
X
H
L
X
CEP
X
X
H
X
L
ACTION ON THE RISING CLOCK EDGE (
Reset (Clear)
Load (Pn
Qn)
)
ORDERING INFORMATION
MC74FXXXAJ Ceramic
MC74FXXXAN Plastic
MC74FXXXAD SOIC
Count (Increment)
No Change (Hold)
No Change (Hold)
LOGIC SYMBOL
9
3
4
5
6
H = HIGH Voltage Level; L = LOW Voltage Level; X = Don’t Care
STATE DIAGRAM
0
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
7
10
2
PE P0 P1 P2 P3
CEP
TC
CET
CP
*R Q0 Q1 Q2 Q3
1
14
13
12
11
15
VCC = PIN 16
GND = PIN 8
*MR for MC74F161A
*SR for MC74F163A
FAST AND LS TTL DATA
4-75
MC74F161A
•
MC74F163A
LOGIC DIAGRAM
P0
PE
MC74F161A
CEP
CET
MC74F163A
ONLY
TC
MC74F163A
P1
P2
P3
CP
CP
MC74F161A
ONLY
Q0
CP
D CP D
CD Q Q
Q0
DETAIL A
DETAIL A
DETAIL A
MR (MC74F161A)
DETAIL A
SR (MC74F163A)
Q0
Q1
Q2
Q3
NOTE:
This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FUNCTIONAL DESCRIPTION
The MC74F161A and MC74F163A count in modulo-16
binary sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven in
parallel through a clock buffer. Thus all changes of the Q out-
puts (except due to Master Reset of the MC74F161A) occur
as a result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous re-
set (MC74F161A), synchronous reset (MC74F163A), parallel
load, count-up and hold. Five control inputs
Master Reset
(MR, MC74F161A), Synchronous Reset (SR, MC74F163A),
Parallel Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle (CET) — determine the mode of operation, as
shown in the Function Table. A LOW signal on MR overrides
all other inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel loading
and allows all outputs to go LOW on the next rising edge of
CP. A LOW signal on PE overrides counting and allows infor-
mation on the Parallel Data (Pn) inputs to be loaded into the
flip-flops on the next rising edge of CP. With PE and MR
(MC74F161A) or SR (MC74F163A) HIGH, CEP and CET per-
mit counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The MC74F161A and MC74F163A use D-type edge-trig-
gered flip-flops and changing the SR, PE, CEP, and CET in-
puts when the CP is in either state does not cause errors, pro-
vided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
FAST AND LS TTL DATA
4-76
MC74F161A
•
MC74F163A
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
74
74
74
74
Min
4.5
0
Typ
5.0
25
Max
5.5
70
– 1.0
20
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
74
74
VOL
IIH
Output LOW Voltage
Input HIGH Current
2.5
2.7
3.4
3.4
0.35
0.5
20
0.1
IIL
IOS
ICC
Input LOW Current
Data, CEP, Clock
PE, CET, SR
Output Short Circuit Current (Note 2)
Power Supply Current
–60
37
–0.6
–1.2
– 150
55
Min
2.0
0.8
–1.2
Typ
Max
Unit
V
V
V
V
V
V
µA
mA
mA
mA
mA
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
IOH = –1.0 mA
IOH = –1.0 mA
IOL = 20 mA
VCC = 4.50 V
VCC = 4.75 V
VCC = MIN
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.5 V
VCC = MAX, VOUT = 0 V
VCC = MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in state 15. To implement synchronous mul-
tistage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways. The TC output is subject
to decoding spikes due to internal race conditions and is there-
fore not recommended for use as a clock or asynchronous
reset for flip-flops, counters, or registers.
Logic Equations:
Count Enable = CEP
•
CET
•
PE
TC = Q0
•
Q1
•
Q2
•
Q3
•
CET
FAST AND LS TTL DATA
4-77
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