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5962F9672101VYC

Description
ACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDFP28
Categorylogic    logic   
File Size489KB,4 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

5962F9672101VYC Overview

ACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDFP28

5962F9672101VYC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeDFP
package instructionDFP, FL28,.4
Contacts28
Reach Compliance Codenot_compliant
Is SamacsysN
seriesACT
JESD-30 codeR-CDFP-F28
JESD-609 codee0
Logic integrated circuit typeERROR DETECTION AND CORRECTION CIRCUIT
Number of digits16
Number of functions1
Number of terminals28
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL28,.4
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
propagation delay (tpd)37 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height2.92 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose300k Rad(Si) V
width12.445 mm
Base Number Matches1
ACTS630MS
January 1996
Radiation Hardened EDAC
(Error Detection and Correction)
Pinouts
28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835
DESIGNATOR CDIP-T28, LEAD FINISH C
TOP VIEW
DEF 1
DB0 2
DB1 3
DB2 4
28 VCC
27 SEF
26 S1
25 S0
24 CB0
23 CB1
22 CB2
21 CB3
20 CB4
19 CB5
18 DB15
17 DB14
16 DB13
15 DB12
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96721 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
-10
Errors/Bit/Day
MEV-cm
2
/mg
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100
DB3 5
DB4 6
DB5 7
DB6 8
DB7 9
DB8 10
DB9 11
DB10 12
DB11 13
GND 14
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)
Description
The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error
detection and correction circuit. It uses a modified Hamming code to
generate a 6-bit check word from each 16-bit data word. The check word
is stored with the data word during a memory write cycle; during a
memory read cycle a 22-bit word is taken form memory and checked for
errors. Single bit errors in the data words are flagged and corrected. Sin-
gle bit errors in check words are flagged but not corrected. The position
of the incorrect bit is pinpointed, in both cases, by the 6-bit error
syndrome code which is output during the error correction cycle.
The ACTS630MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or
a 28 Lead Ceramic Dual-In-Line Package (D suffix).
28 PIN CERAMIC FLATPACK, MIL-STD-1835
DESIGNATOR CDFP3-F28, LEAD FINISH C
TOP VIEW
DEF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
SEF
S1
S0
CB0
CB1
CB2
CB3
CB4
CB5
DB15
DB14
DB13
DB12
Ordering Information
PART NUMBER
5962F9672101VXC
5962F9672101VYC
ACTS630D/Sample
ACTS630K/Sample
ACTS630HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
28 Lead SBDIP
28 Lead Ceramic Flatpack
28 Lead SBDIP
28 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518786
3204.1

5962F9672101VYC Related Products

5962F9672101VYC ACTS630HMSR
Description ACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDFP28 ACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, UUC28, DIE-28
Parts packaging code DFP DIE
package instruction DFP, FL28,.4 DIE,
Contacts 28 28
Reach Compliance Code not_compliant unknown
series ACT ACT
JESD-30 code R-CDFP-F28 R-XUUC-N28
Logic integrated circuit type ERROR DETECTION AND CORRECTION CIRCUIT ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits 16 16
Number of functions 1 1
Number of terminals 28 28
Output characteristics 3-STATE 3-STATE
Package body material CERAMIC, METAL-SEALED COFIRED UNSPECIFIED
encapsulated code DFP DIE
Package shape RECTANGULAR RECTANGULAR
Package form FLATPACK UNCASED CHIP
propagation delay (tpd) 37 ns 37 ns
Certification status Not Qualified Not Qualified
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class V
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount YES YES
technology CMOS CMOS
Terminal form FLAT NO LEAD
Terminal location DUAL UPPER
total dose 300k Rad(Si) V 300k Rad(Si) V
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