PH955L
N-channel TrenchMOS logic level FET
Rev. 02 — 19 February 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC convertors
General purpose power switching
Motors, lamps and solenoids
Portable equipment
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 5 V;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
55
62.5
62.5
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
150 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 25 A;
V
DS
= 44 V; T
j
= 25 °C;
see
Figure 11;
see
Figure 12
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 10
-
16.4
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
6.2
8.3
mΩ
Nexperia
PH955L
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
S
S
S
G
D
Pinning information
Symbol
Description
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
PH955L
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
PH955L_2
Product data sheet
Rev. 02 — 19 February 2009
©
2 of 13
Nexperia B.V. 2017. All rights reserved
Nexperia
PH955L
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)R
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
repetitive drain-source
avalanche energy
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 5 V; I
D
= 4.4 A; V
sup
≤
55 V; unclamped;
t
p
= 0.1 ms; R
GS
= 50
Ω
[1][2]
V
GS
= 5 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 5 V; T
mb
= 25 °C; see
Figure 1;
see
Figure 3
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
-
Max
55
55
20
43.7
62.5
187
62.5
150
150
52
156
2
195
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive
V
GS
= 5 V; T
j(init)
= 25 °C; I
D
= 44 A; V
sup
≤
55 V;
drain-source avalanche unclamped; t
p
= 0.1 ms; R
GS
= 50
Ω
energy
[1]
[2]
Duty cycle is limited by the maximum junction temperature.
Repetitive avalanche failure is not determined simply by thermal effects. Repetitive avalanche transients
should only be applied for short bursts, not every switching cycle.
PH955L_2
Product data sheet
Rev. 02 — 19 February 2009
©
3 of 13
Nexperia B.V. 2017. All rights reserved
Nexperia
PH955L
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa24
120
P
der
(%)
80
03aa16
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aaa777
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 µs
100
µ
s
10
DC
1
1 ms
10 ms
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH955L_2
Product data sheet
Rev. 02 — 19 February 2009
©
4 of 13
Nexperia B.V. 2017. All rights reserved
Nexperia
PH955L
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
2
Unit
K/W
thermal resistance from see
Figure 4
junction to mounting
base
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
-1
0.05
0.02
single pulse
10
-2
t
p
T
P
003aaa778
δ
=
t
p
T
t
10
-3
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PH955L_2
Product data sheet
Rev. 02 — 19 February 2009
©
5 of 13
Nexperia B.V. 2017. All rights reserved
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