Hitachi 16-Bit Microcomputer
H8/3008
Hardware Manual
ADE-602-221
Rev. 1.0
9/14/00
Hitachi, Ltd.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface
The H8/3008 is a high-performance microcontroller that integrates system supporting functions
together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),
an A/D converter, a D/A converter, I/O ports, and other facilities. The two-channel SCI supports a
smart card interface handling ISO/IEC7816-3 character transmission as an expansion function.
Functions have also been added to reduce power consumption in battery-powered applications:
individual modules can be placed in standby mode, and the frequency of the system clock supplied
to the chip can be divided under program control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently for each area, simplifying the connection of different types of memory. Six
MCU operating modes (modes 1 to 4) are provided, offering a choice of initial data bus width and
address space size.
With these features, the H8/3008 enables easy implementation of compact, high-performance
systems.
This manual describes the H8/3008 hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Contents
Section 1 Overview
..............................................................................................................
1.1
1.2
1.3
Overview ............................................................................................................................
Block Diagram....................................................................................................................
Pin Description ...................................................................................................................
1.3.1 Pin Arrangement ...................................................................................................
1.3.2 Pin Functions.........................................................................................................
1.3.3 Pin Assignments in Each Mode ............................................................................
1
1
5
6
6
9
13
Section 2 CPU
........................................................................................................................ 17
2.1
Overview ............................................................................................................................
2.1.1 Features .................................................................................................................
2.1.2 Differences from H8/300 CPU..............................................................................
CPU Operating Modes .......................................................................................................
Address Space ....................................................................................................................
Register Configuration .......................................................................................................
2.4.1 Overview ...............................................................................................................
2.4.2 General Registers ..................................................................................................
2.4.3 Control Registers...................................................................................................
2.4.4 Initial CPU Register Values ..................................................................................
Data Formats ......................................................................................................................
2.5.1 General Register Data Formats .............................................................................
2.5.2 Memory Data Formats ..........................................................................................
Instruction Set ....................................................................................................................
2.6.1 Instruction Set Overview ......................................................................................
2.6.2 Instructions and Addressing Modes ......................................................................
2.6.3 Tables of Instructions Classified by Function.......................................................
2.6.4 Basic Instruction Formats......................................................................................
2.6.5 Notes on Use of Bit Manipulation Instructions ....................................................
Addressing Modes and Effective Address Calculation......................................................
2.7.1 Addressing Modes.................................................................................................
2.7.2 Effective Address Calculation...............................................................................
Processing States ................................................................................................................
2.8.1 Overview ...............................................................................................................
2.8.2 Program Execution State .......................................................................................
2.8.3 Exception-Handling State .....................................................................................
2.8.4 Exception Handling Operation..............................................................................
2.8.5 Bus-Released State................................................................................................
2.8.6 Reset State .............................................................................................................
2.8.7 Power-Down State ................................................................................................
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i
2.2
2.3
2.4
2.5
2.6
2.7
2.8
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