ML145554
ML145564
ML145557
ML145567
PCM Codec–Filter
Legacy Device:
Motorola MC145554, MC145557, MC145564, MC145567
The ML145554, ML145557, ML145564, and ML145567 are all per channel
PCM Codec–Filters. These devices perform the voice digitization and recon-
struction as well as the band limiting and smoothing required for PCM sys-
tems. They are designed to operate in both synchronous and asynchronous
applications and contain an on–chip precision voltage reference. The
ML145554 (Mu–Law) and ML145557 (A–Law) are general purpose devices
that are offered in 16–pin packages. The ML145564 (Mu–Law) and
ML145567 (A–Law), offered in 20–pin packages, add the capability of analog
loopback and push–pull power amplifiers with adjustable gain.
These devices have an input operational amplifier whose output is the input
to the encoder section. The encoder section immediately low–pass filters the
analog signal with an active R–C filter to eliminate very–high–frequency noise
from being modulated down to the pass band by the switched capacitor filter.
From the active R–C filter, the analog signal is converted to a differential sig-
nal. From this point, all analog signal processing is done differentially. This
allows processing of an analog signal that is twice the amplitude allowed by a
single–ended design, which reduces the significance of noise to both the invert-
ed and non–inverted signal paths. Another advantage of this differential design
is that noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band-
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized-
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A con-
verter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X com-
pensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
These PCM Codec–Filters accept both long–frame and short–frame industry
standard clock formats. They also maintain compatibility with Motorola’s fami-
ly of TSACs and MC3419/MC34120 SLIC products.
The ML145554/57/64/67 family of PCM Codec–Filters utilizes CMOS due
to its reliable low–power performance and proven capability for complex
analog/digital VLSI functions.
FEATURES
ML145554/57(16–Pin Package)
• Fully Differential Analog Circuit Design for Lowest Noise
• Performance Specified for Extended Temperature Range of – 40 to + 85°C
• Transmit Band–Pass and Receive Low–Pass Filters On–Chip
• Active R–C Pre–Filtering and Post–Filtering
• Mu–Law Companding ML145554
• A–Law Companding ML145557
• On–Chip Precision Voltage Reference (2.5 V)
• Typical Power Dissipation of 40 mW, Power Down of 1.0 mW at ±5 V
ML145564/67(20–Pin Package) — All of the Features of the ML145554/57 Plus:
• Mu–Law Companding ML145564
• A–Law Companding ML145567
• Push–Pull Power Drivers with External Gain Adjust
• Analog Loopback
Page 1 of 18
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Issue
16
1
P DIP 16 = EP
PLASTIC DIP
CASE 648
ML145554/57
SOG 16 = -5P
SOG PACKAGE
CASE 751G
ML145554/57
16
1
20
1
P DIP 20 = RP
PLASTIC DIP
CASE 738
ML145564/67
SOG 20 = -6P
SOG PACKAGE
CASE 751D
ML145564/67
20
1
CROSS REFERENCE/ORDERING INFORMATION
LANSDALE
PACKAGE
MOTOROLA
P DIP 16
SO 16W
P DIP 16
SO 16W
P DIP 20
SO 20W
P DIP 20
SO 20W
MC145554P
MC145554DW
MC145557P
MC145557DW
MC145564P
MC145564DW
MC145567P
MC145567DW
ML145554EP
ML145554-5P
ML145557EP
ML145557-5P
ML145564RP
ML145564-6P
ML145567RP
ML145567-6P
Note:
Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from
ML
to
MLE.
ML145554, ML145557, ML145564, ML145567
PIN ASSIGNMENTS
ML145554, ML145557
VBB
GNDA
VFRO
VCC
FSR
DR
BCLKR/ CLKSEL
MCLKR/ PDN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VFXI +
VFXI –
GSX
TSX
FSX
DX
BCLKX
MCLKX
LANSDALE Semiconductor, Inc
ML145564, ML145567
VPO +
GNDA
VPO –
VPI
VFRO
VCC
FSR
DR
BCLKR/ CLKSEL
MCLKR/ PDN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VBB
VFXI +
VFXI –
GSX
ANLB
TSX
FSX
DX
BCLKX
MCLKX
FUNCTIONAL BLOCK DIAGRAM
MCLKR/ BCLKR/
PDN
CLKSEL
GSX
ANLB
*
VCC
GNDA VBB
FSX
FSR MCLKX BCLKX
VFXI –
VFXI +
–
+
RC ACTIVE
LOW–PASS
FILTER
5–POLE SC
LOW–PASS
FILTER
3–POLE
HIGH–PASS
AND S/H
COMP
INTERNAL SEQUENCING
AND CONTROL
TSX
VPO +
*
–1
BAND–GAP
VOLTAGE
REF
–
4
RDAC
CDAC
8
SAR
REG
TRANSMIT
SHIFT
REG
DX
VPO –
*
4
+
MUX
RECEIVE
SHIFT
REG
VPI
*
RC ACTIVE
LOW–PASS
FILTER
5–POLE SC
LOW–PASS
FILTER
8
S/H
RECEIVE
LATCH
DR
VFRO
* ML145564 and ML145567 only.
Page 2 of 18
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Issue
LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML14556
DEVICE DESCRIPTION
A codec–filter is used for digitizing and reconstructing the-
human voice. These devices were developed primarily for the
telephone network to facilitate voice switching and transmis-
sion. Once the voice is digitized, it may be switched by digital
switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from “COder” (for the A/D used to digi-
tize voice) and “DECoder” (for the D/A used for reconstruct-
ing voice). A codec is a single device that does both the A/D
and D/A conversions.
To digitize intelligible voice requires a signal–to–distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This can be accomplished with a linear 13–bit A/D and D/A,
but will far exceed the required signal–to–distortion ratio at
amplitudes greater than 40 dB below the peak amplitude. This
excess performance is at the expense of data per sample.
Methods of data reduction are implemented by compressing
the 13–bit linear scheme to companded 8–bit schemes. There
are two companding schemes used: Mu–255 Law specifically
in North America, and A–Law specifically in Europe. These
companding schemes are accepted world wide. These com-
panding schemes follow a segmented or “piecewise–linear”
curve formatted as sign bit, three chord bits, and four step bits.
For a given chord, all sixteen of the steps have the same volt-
age weighting. As the voltage of the analog input increases, the
four step bits increment and carry to the three chord bits which
increment. When the chord bits increment, the step bits double
their voltage weighting. This results in an effective resolution
of six bits (sign + chord + four step bits) across a 42 dB
dynamic range (seven chords above zero, by 6 dB per chord).
Tables 3 and 4 show the linear quantization levels to PCM
words for the two companding schemes.
In a sampling environment, Nyquist theory says that to prop-
erly sample a continuous signal, it must be sampled at a fre-
quency higher than twice the signal’s highest frequency com-
ponent. Voice contains spectral energy above 3 kHz, but its
absence is not detrimental to intelligibility. To reduce the digi-
tal data rate, which is proportional to the sampling rate, a sam-
ple rate of 8 kHz was adopted, consistent with a bandwidth of
3 kHz. This sampling requires a low–pass filter to limit the
high frequency energy above 3 kHz from distorting the
in–band signal. The telephone line is also subject to 50/60 Hz
power line coupling, which must be attenuated from the signal
by a high–pass filter before the A/D converter.
The D/A process reconstructs a staircase version of the
desired in–band signal, which has spectral images of the
in–band signal modulated about the sample frequency and its
harmonics. These spectral images, called aliasing components,
need to be attenuated to obtain the desired signal. The
low–pass filter used to attenuate these aliasing components is
typically called a reconstruction or smoothing filter.
The ML145554/57/64/67 PCM Codec–Filters have the
codec, both presampling and reconstruction filters, and a pre-
cision voltage reference on–chip, and require no external com-
ponents.
PIN
DESCRIPTION
DIGITAL
FSR
Receive Frame Sync
This is an 8 kHz enable that must be synchronous with
BCLKR. Following a rising FSR edge, a serial PCM word at
DR is clocked by BCLKR into the receive data register. FSR
also initiates a decode on the previous PCM word. In the ab-
sence of FSX, the length of the FSR pulse is used to deter-
mine whether the I/O conforms to the Short Frame Sync or
Long Frame Sync convention.
DR
Receive Digital Data Input
BCLKR/CLKSEL
Receive Data Clock and Master Clock Frequency Selector
If this input is a clock, it must be between 128 kHz and
4.096 MHz, and synchronous with FSR. In synchronous appli
cations this pin may be held at a constant level; then BCLKX
is used as the data clock for both the transmit and receive
sides, and this pin selects the assumed frequency of the master
clock (see Table 1 in
Functional Description).
MCLKR/PDN
Receive Master Clock and
Power–Down
Control
Because of the shared DAC architecture used on these
devices, only one master clock is needed. Whenever FSX is
clocking, MCLKX is used to derive all internal clocks, and the
MCLKR/PDN pin merely serves as a power–down control. If
MCLKR/PDN pin is held low or is clocked (and at least one o
the frame syncs is present), the part is powered up. If this pin
is held high, the part is powered down. If FSX is absent but
FSR is still clocking, the device goes into receive half–channe
mode, and MCLKR (if clocking) generates the internal clocks
MCLKX
Transmit Master Clock
This clock is used to derive the internal sequencing clocks; i
must be 1.536 MHz, 1.544 MHz, or 2.048 MHz.
BCLKX
Transmit Data Clock
BCLKX may be any frequency between 128 kHz and 4.096
MHz, but it should be synchronous with MCLKX.
DX
Transmit Digital Data Output
This output is controlled by FSX and BCLKX to output the
PCM data word; otherwise this pin is in a high–impedance state
FSX
Transmit Frame Sync
This is an 8 kHz enable that must be synchronous
with BCLKX. A rising FSX edge initiates the transmission of
Page 3 of 18
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ML145554, ML145557, ML145564, ML145567
LANSDALE Semiconductor, Inc
serial PCM word, clocked by BCLKX, out of DX. If the FSX
pulse is high for more than eight BCLKX periods, the DX and
TSX outputs will remain in a low–impedance state until FSX is
brought low. The length of the FSX pulse is used to determine
whether the transmit and receive digital I/O conforms to the
Short Frame Sync or to the Long Frame Sync convention.
TSX
Transmit Time Slot Indicator
This is an open–drain output that goes low whenever the DX
output is in a low–impedance state (i.e., during the transmit
time slot when the PCM word is being output) for enabling a
PCM bus driver.
ANLB
Analog Loopback Control Input (ML145564/67 Only)
When held high, this pin causes the input of the transmit RC
active filter to be disconnected from GSX and connected to
VPO+ for analog loopback testing. This pin is held low in
normal operation.
ANALOG
GSX
Gain–Setting Transmit
This output of the transmit gain–adjust operational amplifi-
er is internally connected to the encoder section of the device.
It must be used in conjunction with VFXI– and VFXI+ to set
the transmit gain for a maximum signal amplitude of 2.5 V
peak. This output can drive a 600
Ω
load to 2.5 V peak.
VFXI–
Voice–Frequency Transmit Input (Inverting)
This is the inverting input of the transmit gain–adjust
operational amplifier.
VFXI+
Voice–Frequency Transmit Input (Non–Inverting)
This is the non–inverting input of the transmit gain–adjust
operational amplifier.
VFRO
Voice–Frequency Receive Output
This receive analog output is capable of driving a 600
Ω
load
to 2.5 V peak.
VPI
Voltage
Power
Input (ML145564/67 Only)
This is the inverting input to the first receive power ampli-
fier. Both of the receive power amplifiers can be powered
down by connecting this input to VBB.
VPO–
Voltage
Power
Output (Inverted) (ML145564/67 Only)
This inverted output of the receive push–pull power ampli-
fiers can drive 300
Ω
to 3.3 V peak.
VPO+
Voltage
Power
Output (Non–Inverted) (ML145554/67 Only)
This non–inverted output of the receive push–pull power
Page 4 of 18
amplifier pair can drive 300
Ω
to 3.3 V peak.
POWER
SUPPLY
GNDA
Analog Ground
This terminal is the reference level for all signals, both ana-
log and digital. It is 0 V.
VCC
Positive Power
Supply
VCC is typically 5 V.
VBB
Negative
Power
Supply
VBB is typically – 5 V.
FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL
PATH
The transmit portion of these codec–filters includes a
low–noise gain setting amplifier capable of driving a 600
Ω
load. Its output is fed to a three–pole anti–aliasing pre–filter
This pre–filter incorporates a two–pole Butterworth active
low–pass filter, and a single passive pole. This pre–filter is
followed by a single ended–to–differential converter that is
clocked at 256 kHz. All subsequent analog processing uti-
lizes fully differential circuitry. The next section is a
fully–differential, five–pole switched capacitor low–pass fil
ter with a 3.4 kHz passband. After this filter is a 3–pole
switched–capacitor high–pass filter having a cutoff frequen-
cy of about 200 Hz. This high–pass stage has a transmission
zero at DC that eliminates any DC coming from the analog
input or from accumulated operational amplifier offsets in
the preceding filter stages. The last stage of the high–pass
filter is an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and
digital–to–analog converter (DAC) are shared by the transm
and receive sections. The autozeroed, switched–capacitor
bandgap reference generates precise positive and negative
reference voltages that are independent of temperature and
power supply voltage. A binary–weighted capacitor array
(CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame–by–frame autozeroed com-
parator to implement a successive–approximation conversion
algorithm. All of the analog circuitry involved in the data
conversion the voltage reference, RDAC, CDAC, and com-
parator are implemented with a differential architecture.
The receive section includes the DAC described above,
asample and hold amplifier, a five–pole 3400 Hz switched-
capacitor low–pass filter with sinX/X correction, and a
two–pole active smoothing filter to reduce the spectral com-
ponents of the switched capacitor filter. The output of the
smoothing filter is a power amplifier that is capable of driv-
ing a 600
Ω
load. The ML145564 and ML145567 add a pair
of power amplifiers that are connected in a push–pull con-
figuration; two external resistors set the gain of both of the
www.lansdale.com
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LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML14556
complementary outputs. The output of the second amplifier may be
internally connected to the input of the transmit anti–aliasing filter by
bringing the ANLB pin high. The power amplifiers can drive unbal-
anced 300
Ω
loads or a balanced 600
Ω
load; they may be powered
down independent of the rest of the chip by tying the VPI pin to
VBB.
MASTER CLOCKS
Since the codec–filter design has a single DAC architecture, only
one master clock is used. In normal operation (both frame syncs
clocking), the MCLKX is used as the master clock, regardless of
whether the MCLKR/PDN pin is clocking or low. The same is true if
the part is in transmit half–channel mode (FSX clocking, FSR held
low). But if the codec–filter is in the receive half–channel mode, with
FSR clocking and FSX held low, MCLKR is used for the internal
master clock if it is clocking; if MCLKR is low, then MCLKX is still
used for the internal master clock. Since only one of the master
clocks isused at any given time, they need not be synchronous.
The master clock frequency must be 1.536 MHz, 1.544 MHz, or
2.048 MHz. The frequency that the codec–filter expects depends
upon whether the part is a Mu–Law or an A–Law part, and on the
state of the BCLKR/CLKSEL pin.The allowable options are shown
In Table 1. When a level (rather than a clock) is provided for
BCLKR/CLKSEL, BCLKX is used as the bit clock for both transmit
and receive.
Table 1. Master Clock Frequency Determination
Master Clock Frequency Expected
BCLKR/CLKSEL
Clocked, 1, or Open
0
ML145554/64
1.536 MHz
1.544 MHz
2.048 MHz
ML145557/67
2.048 MHz
1.536 MHz
1.544 MHz
high, the sign bit appears at the DX output. The next seven rising
edges of BCLKX clock out the remaining seven bits of the PCM
word. The DX and TSX outputs return to a high impedance state on
the falling edge of the eighth bit clock or the falling edge of FSX,
whichever comes later. The receive PCM word is clocked into DR on
the eight falling BCLKR edges following an FSR rising edge.
For Short Frame Sync operation, the frame sync pulses must be
one bit clock period long. On the first BCLKX rising edge after the
falling edge of BCLKX has latched FSX high, the DX and TSX out-
puts are enabled and the sign bit is presented on DX. The next seven
rising edges of BCLKX clock out the remaining seven bits of the
PCM word; on the eighth BCLKX falling edge, the DX and TSX
outputs return to a high impedance state. On the second falling
BCLKR edge following an FSR rising edge, the receive sign bit is
clocked into DR. The next seven BCLKR falling edges clock in the
remaining seven bits of the receive PCM word.
Table 2 shows the coding format of the transmit and receive PCM
words.
HALF–CHANNEL MODES
FRAME SYNCS AND DIGITAL I/O
These codec–filters can accommodate both of the industry standard
timing formats. The Long Frame Sync mode isused by Lansdale’s
ML145500 family of codec–filters and the UDLT family of digital
loop transceivers. The Short Frame Sync mode is compatible with the
IDL (Interchip Digital Link) serial format used in Motorola and
Lansdale’s ISDN family and by other companies in their telecommu-
nication devices. These codec–filters use the length of the transmit
frame sync (FSX) to determine the timing format for both transmit
and receive unless the part is operating in the receive half–channel
mode.
In the Long Frame Sync mode, the frame sync pulses must be at
least three bit clock periods long. The DX and TSX outputs are
enabled by the logical ANDing of FSX and BCLKX; when both are
Mu–Law (ML145554/64)
Level
+ Full Scale
+ Zero
– Zero
– Full Scale
Sign Bit
1
1
0
0
Chord Bits
000
111
111
000
In addition to the normal full–duplex operating mode, these
codec–filters can operate in both transmit and receive half–channel
modes. Transmit half–channel mode is entered by holding FSR low.
The VFRO output goes to analog ground but remains in a low imped
ance state (to facilitate a hybrid interface); PCM data at DR is
ignored. Holding FSX low while clocking FSR puts these devices in
the receive half–channel mode. In this state, the transmit input oper-
ational amplifier continues to operate, but the rest of the transmit cir-
cuitry is disabled; the DX and TSX outputs remain in a high imped-
ance state. MCLKR is used as the internal master clock if it is clock-
ing. If MCLKR is not clocking, then MCLKX is used for the interna
master clock, but in that case it should be synchronous with FSR. If
BCLKR is not clocking, BCLKX will be used for the receive data,
just as in the full–channel operating mode. In receive half–channel
mode only, the length ofthe FSR pulse is used to determine whether
Short Frame Sync or Long Frame Sync timing is used at DR.
POWER–DOWN
Holding both FSX and FSR low causes the part to go into the
power–down state. Power–down occurs approximately 2 ms after the
last frame sync pulse is received. An alternative way to put these
devices in power–down is to hold the MCLKR/PDN pin high. When
the chip is powered down, the DX, TSX, and GSX outputs are high
impedance, the VFRO, VPO–, and VPO+ operational amplifiers are
biased with a trickle current so that their respective outputs remain
stable at analog ground. To return the chip to the power–up state,
MCLKR/PDN must be low or clocking and at least one of the frame
sync pulses must be present. The DX and TSX outputs will remain in
a high–impedance state until the second FSX pulse after power–up.
Table 2. PCM Data Format
A–Law (ML145557/67)
Sign Bit
1
1
0
0
Chord Bits
010
101
101
010
Step Bits
1010
0101
0101
1010
0000
1111
1111
0000
Step Bits
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Analog electronics
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