LCS700-708
HiperLCS
™
Family
Integrated LLC Controller, High-Voltage
Power MOSFETs and Drivers
Product Highlights
Features
•
LLC half-bridge power stage incorporating controller, high and
low-side gate drives, and high-voltage power MOSFETs
•
Eliminates up to 30 external components
•
High maximum operating frequency of 1 MHz
•
Nominal steady-state operation up to 500 kHz
•
Dramatically reduces magnetics size and allows use of
SMD ceramic output capacitors
•
Precise duty symmetry balances output rectifier current,
improving efficiency
•
50% ±0.3% typical at 300 kHz
•
Comprehensive fault handling and current limiting
•
Programmable brown-in/out thresholds and hysteresis
•
Undervoltage (UV) and overvoltage (OV) protection
•
Programmable over-current protection (OCP)
•
Short-circuit protection (SCP)
•
Over-temperature protection (OTP)
•
Programmable dead-time for optimized design
•
Programmable burst mode maintains regulation at no-load and
improves light load efficiency
•
Programmable soft-start time and delay before soft-start
•
Accurate programmable minimum and maximum frequency
limits
•
Single package designed for high-power and high-frequency
•
Reduces assembly cost and reduces PCB layout loop areas
•
Simple single clip attachment to heat sink
•
Exposed thermal pad connected to ground potential – no
insulators required between package and heat sink
•
Staggered pin arrangement for simple PC board routing
and high-voltage creepage requirements
•
Paired with HiperPFS PFC product gives complete, high
efficiency, low part count PSU solutions
Applications
•
High-efficiency power supplies (80 PLUS Silver, Gold and
Platinum)
•
LCD TV power supplies
•
LED street and area lighting
•
Printer power supplies
•
Audio amplifier
Description
The HiperLCS is an integrated LLC power stage incorporating a
multi-function controller, high-side and low-side gate drivers,
plus two power MOSFETs in a half-bridge configuration. Figure
1 shows a simplified schematic of a HiperLCS based power stage
where the LLC resonant inductor is integrated into the transformer.
The variable frequency controller provides high efficiency by
switching the power MOSFETs at zero voltage (ZVS), eliminating
switching losses.
B+
VCCH
D
Standby
Supply
VCC
CONTROL
HB
+V
HV DC
Input
OV/UV
VREF
R
FMAX
DT/BF
IS
RTN
R
BURST
FB
G
S1/S2
HiperLCS
B-
LLC Feedback Circuit
PI-6159-060211
Figure 1.
Typical Application Circuit – LCD TV and PC Main Power Supply.
Output Power Table
Product
LCS700HG
LCS701HG
LCS702HG
LCS703HG
LCS705HG
LCS708HG
Maximum Practical Power
1
110 W
170 W
220 W
275 W
350 W
440 W
Table 1. Output Power Table.
Notes:
1. Maximum practical power is the power the part can deliver when properly
mounted to a heat sink and a maximum heat sink temperature of 90 °C.
www.powerint.com
June 2011
LCS700-708
Pin Functional Description
VCC Pin
IC power pin. In a typical application, VCC is connected to the
12 V system standby supply via a 5
W
resistor. This resistor
helps provide filtering and improves noise immunity.
Note: The system standby supply return should be connected to
the B- bus and not to the GROUND pin.
VREF Pin
3.4 VREF pin. An internal voltage reference network used as a
voltage source for FEEDBACK pin and DT/BF pin pull-up
resistor.
GROUND (G) Pin
G is the return node for all analog small signals. All small signal
pin bypass capacitors must be returned to this pin through short
traces, with the exception of the D-S high-voltage bypass
capacitor, and the VCCH bypass capacitor. It is internally
connected to the SOURCE pins to provide a star connection.
Do not connect the GROUND pin to the SOURCE pins,
nor to the B- bus, in the PCB layout.
OV/UV Pin
Overvoltage/Undervoltage pin. B+ is sensed by this pin through
a resistor divider. The OV/UV pin implements brown-in,
brown-out, and overvoltage lockout with hysteresis. Pulling this
pin down to ground will implement a remote-off function.
FEEDBACK (FB) Pin
Current fed into this pin determines LLC switching frequency;
higher current programs higher switching frequency. The pin
V-I characteristic resembles a diode to ground during normal
switching. An RC network between the VREF pin and
FEEDBACK pin determines the minimum operating frequency,
start-up frequency, soft-start time, and delay before start-up.
DEAD-TIME/BURST FREQUENCY (DT/BF) Pin
A resistor divider from VREF to ground programs dead-time,
maximum switching frequency at start-up, and burst-mode
threshold frequencies.
CURRENT-SENSE (IS) Pin
The CURRENT-SENSE pin is used for sensing transformer
primary current, to detect overload and fault conditions, through
a current sense resistor or a capacitive divider plus sense resistor
circuit. It resembles a reverse diode to ground, and does not
require a rectifier circuit for preventing negative pulses from
reaching the pin, provided the reverse current is limited to <5 mA.
Figure 3.
Pin Numbering and Designation.
H Package (eSIP-16C)
Exposed Metal
(On Package Edge)
1
Internally
Connected
VCCH
3 4 5 6 7 8 9 1011 13 14 16
S2
S1
NC
IS
DT/BF
FB
OV/UV
G
VREF
HB
G
G
VCCH
HB
D
NC
VCC
D
D
Exposed Pad
(Backside) Internally
Connected to GROUND
Pin (see eSIP-16C
Package Drawing)
PI-5636-051311
SOURCE (S1), (S2) Pins
SOURCE pins of internal low-side MOSFET. These should be
connected together on the PCB, and connected to the B- from
the PFC bulk capacitor or input high-voltage DC return.
HB Pin
This is the output of the half-bridge connected MOSFETs
(Source of high-side MOSFET, Drain of low-side MOSFET), to
be connected to the LLC power train (transformer primary and
series resonant capacitor).
VCCH Pin
Floating bootstrap supply pin for the LLC high-side driver. This
pin is referenced to the HB pin, which in turn is internally
connected to the SOURCE pin of the high-side MOSFET. A
bypass/storage capacitor between VCCH and HB pins, and a
boot strap diode with a series resistor from the standby supply,
are required. The storage capacitor is refreshed every time the
lower MOSFET turns on or its body diode conducts.
DRAIN (D) Pin
DRAIN pin of the internal high-side MOSFET. This connects to
the B+ from the PFC bulk capacitor or input high-voltage DC bus.
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Rev. B 062011
LCS700-708
HiperLCS Basic Operation
The HiperLCS is designed for half-bridge LLC converters, which
are high-efficiency resonant, variable frequency converters. The
HiperLCS is an LLC controller chip with built-in drivers and
half-bridge MOSFETs.
LLC converters require a fixed dead-time between switching
half-cycles. The dead-time, maximum frequency at start-up,
and burst threshold frequencies, are programmed with a resistor
divider on the DT/BF pin from the VREF to the GROUND pins.
The FEEDBACK (FB) pin is the frequency control input for the
feedback loop. Frequency is proportional to FEEDBACK pin
current. The FEEDBACK pin V-I characteristic resembles a
diode to ground.
Burst Mode
If the frequency commanded by the FEEDBACK pin current
exceeds the upper burst threshold frequency (f
STOP
, I
STOP
)
programmed by the resistor divider on the DT/BF pin, the output
MOSFETs will turn off, and will resume switching when the current
drops below the value which corresponds to the frequency
equal to the lower burst threshold frequency (f
START
, I
START
). As a
first approximation, burst mode control resembles a hysteretic
controller where the frequency ramps from f
START
to f
STOP
, stops
and repeats. An external component network connected from
the VREF pin to the FEEDBACK pin determines the minimum
and start-up FEEDBACK pin currents, and thus the minimum
and start-up switching frequencies. A soft-start capacitor in
this network determines soft-start timing.
The VREF pin provides a nominal 3.4 V as a reference for this
FEEDBACK pin external network and other functions. Maximum
current from this pin must be ≤4 mA.
The Dead-Time/Burst Frequency (DT/BF) pin also has a diode-to-
ground V-I characteristic. A resistor divider from VREF to GROUND
programs dead-time, maximum start-up switching frequency (f
MAX
),
and the burst threshold frequencies. The current flowing from the
resistor divider to the DT/BF pin determines f
MAX
. The ratio of the
resistors selects from 3 discrete, burst threshold frequency ratios,
which are fixed fractions of f
MAX
.
The OV/UV pin senses the high-voltage B+ input through a
resistor divider. It implements brown-in, brown-out, and OV
with hysteresis. The ratios of these voltages are fixed; the user
must select the resistor divider ratio such that the brown-in
voltage is below the minimum nominal bulk (input) voltage
regulation set-point to ensure start-up, and the OV (lower)
restart voltage is above the maximum nominal bulk voltage
set-point, to ensure that the LCS will restart after a voltage swell
event that triggers the OV upper threshold. If different brown-in
to brown-out to OV ratios are required, external circuitry needs
to be added to the resistor divider.
VCC Pin UVLO
The VCC pin has an internal UVLO function with hysteresis. The
HiperLCS will not start until the voltage exceeds the VCC start
threshold V
UVLO(+)
. HiperLCS will turn off when the VCC drops to
the VCC Shutdown Threshold V
UVLO(-)
.
VCCH Pin UVLO
The VCCH pin is the supply pin for the high-side driver. It also
has a UVLO function similar to the VCC pin, with a threshold
lower than the VCC pin. This is to allow for a VCCH voltage that
is slightly lower than VCC because the VCCH pin is fed by a
bootstrap diode and series current-limiting resistor from the
VCC supply.
Start-Up and Auto-Restart
Before start-up the FEEDBACK pin is internally pulled up to the
VREF pin to discharge the soft-start capacitor and to keep the
output MOSFETs off. When start-up commences the internal
pull-up transistor turns off, the soft-start capacitor charges, the
outputs begin switching at f
MAX
, the FEEDBACK pin current
diminishes, the switching frequency drops, and the PSU output
rises. When the output reaches the voltage set-point, the
optocoupler will conduct, closing the loop and regulating the output.
Whenever the VCC pin is powered up, the DT/BF pin goes into
high impedance mode for 500
ms
in order to sense the voltage
divider ratio and select the Burst Threshold. This setting is
stored until the next VCC recycle. The DT/BF pin then goes into
normal mode, resembling a diode to ground, and the sensed
current continuously sets the f
MAX
frequency. The burst threshold
frequencies are fixed fractions of f
MAX
. The internal oscillator
runs the internal counters at f
MAX
whenever the FEEDBACK pin
internal pull-up is on.
When a fault is detected on the IS, OV/UV, or VCC pin (UVLO),
the internal FEEDBACK pin pull-up transistor turns on for
131,072 clock cycles, to discharge the soft-start capacitor
completely, then a restart is attempted. The first power-up after
a VCC recycle only waits 1024 cycles, including the condition
where the OV/UV pin rises above the brown-in voltage for the
first time, after VCC is powered up.
Remote-Off
Remote-off can be invoked by pulling down the OV/UV pin to
ground, or by pulling up the IS pin to >0.9 V. Both will invoke a
131,072 cycle restart cycle. VCC can also be pulled down to
shut the device off, but when it is pulled up, the FEEDBACK pin
is pulled up to the VREF pin to discharge the soft-start capacitor
for only 1024 f
MAX
clock cycles. If this scheme is used, the
designer must ensure that the time the VCC is pulled down,
plus 1024 cycles, is sufficient to discharge the soft-start
capacitor, or if not, that the resulting lower starting frequency is
high enough so as not to cause excessive primary currents that
may cause the over-current protection to trip.
Current Sense
The IS pin senses the primary current. It resembles a reverse
diode to the GROUND pin. It is tolerant of negative voltages
provided the negative current is limited to <5 mA. Therefore it
must be connected to the current sense resistor (or primary
capacitive voltage divider + sense resistor) via a series current
limiting resistor of >220
W.
Thus it can accept an AC waveform
and does not need a rectifier or peak detector circuit. If the IS
pin senses a nominal positive peak voltage of 0.5 V for 7
consecutive cycles, an auto-restart will be invoked. The IS pin
also has a second, higher threshold at nominally 0.9 V, which
will invoke an auto-restart with a single pulse. The minimum
5
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