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MT5C1008ECA-55L/IT

Description
Standard SRAM, 128KX8, 45ns, CMOS, CQCC32, CERAMIC, LCC-32
Categorystorage    storage   
File Size240KB,17 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

MT5C1008ECA-55L/IT Overview

Standard SRAM, 128KX8, 45ns, CMOS, CQCC32, CERAMIC, LCC-32

MT5C1008ECA-55L/IT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeQFJ
package instructionQCCN, LCC32,.45X.55
Contacts32
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
Maximum access time45 ns
Other featuresTTL COMPATIBLE INPUTS/OUTPUTS, 2V DATA RETENTION, BATTERY BACKUP, LOW POWER STANDBY
I/O typeCOMMON
JESD-30 codeR-CQCC-N32
JESD-609 codee0
length13.97 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Encapsulate equivalent codeLCC32,.45X.55
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height3.048 mm
Maximum standby current0.001 A
Minimum standby current2 V
Maximum slew rate0.115 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.43 mm
Base Number Matches1
SRAM
Austin Semiconductor, Inc.
128K x 8 SRAM
WITH DUAL CHIP ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MT5C1008
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin CSOJ (SOJ)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
FEATURES
High Speed: 12, 15, 20, 25, 30, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE1\, CE2, and OE\
options.
• All inputs and outputs are TTL compatible
32-Pin LCC (ECA)
4 3 2 1 32 31 30
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
• 2V data retention/low power
MARKING
-12 (contact factory)
-15
-20
-25
-35
-45
-55*
-70*
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
A12
A14
A10
6
NC
V
CC
A15
CE2
32-Pin Flat Pack (F)
29
28
27
26
25
24
23
22
21
WE
\
A13
A8
A9
A11
OE
\
A10
CE1
\
DQ8
14 15 16 17 18 19 20
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
GENERAL DESCRIPTION
The MT5C1008 SRAM employs high-speed, low power
CMOS designs using a four-transistor memory cell, and are
fabricated using double-layer metal, double-layer polysilicon
technology.
For design flexibility in high-speed memory
applications, this device offers dual chip enables (CE1\, CE2)
and output enable (OE\). These control pins can place the
outputs in High-Z for additional flexibility in system design.
All devices operate from a single +5V power supply and all
inputs and outputs are fully TTL compatible.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled, allowing system designs to
achieve low standby power requirements.
The “L” version offers a 2V data retention mode, re-
ducing current consumption to 1mA maximum.
C
CW
EC
ECA
F
DCJ
SOJ
L
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1008
Rev. 5.5 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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