MC10E411
5V ECL 1:9 Differential
PECL/NECL RAMBus Clock
Buffer
Description
The MC10E411 is a low skew 1-to-9 differential driver, designed
with clock distribution in mind. The MC10E411’s function and
performance are similar to the popular MC10E111, with the added
feature of 1.2 V output swings.
The output voltage swing of the E411 is larger than a standard ECL
swing. The 1.2 V output swings provide a signal which can be AC
coupled into RAMBus compatible input loads. The larger output
swings are produced by lowering the V
OL
of the device. With the
exception of the lower V
OL
, the E411 is identical to the MC10E111.
Note that the larger output swings eliminate the possibility of
temperature compensated outputs, thus the E411 is only available in
the 10E style of ECL. In addition, because the V
OL
is lower than
standard ECL, the outputs cannot be terminated to
−2.0
V. This data
sheet provides a few termination alternatives.
The device TPD is affected by the quantity of output pairs
terminated with minimum occurring with only one output pair and
increasing about 10
−
20 ps for all output pairs. Relative skew
distribution is not affected as more pairs are terminated, but the
increased TPD does shift the entire distribution. Unused output pairs
should be left unterminated (open) to reduce power and switching
noise.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MC10E411FNG
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
•
•
•
•
•
•
200 ps Part-to-Part Skew
50 ps Output-to-Output Skew
Differential Design
V
BB
Output
Voltage Compensated Outputs
PECL Mode Operating Range:
V
CC
= 4.5 V to 5.5 V with V
EE
= 0 V
•
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
−4.5
V to
−5.5
V
•
Internal Input 50 kW Pulldown Resistors
•
ESD Protection: Human Body Model; > 2 kV,
•
•
•
•
•
Machine Model; > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78
IC Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 180 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 8
1
Publication Order Number:
MC10E411/D
MC10E411
Q
0
25
V
EE
EN
IN
V
CC
IN
V
BB
NC
26
27
28
1
2
3
4
5
Q
8
6
Q
8
7
8
9
10
Q
6
11
Q
6
Pinout: 28-Lead PLCC
(Top View)
Q
0
24
Q
1
V
CCO
Q
1
23
22
21
Q
2
20
Q
2
19
18
17
16
15
14
13
12
Q
3
Q
3
Q
4
V
CCO
Q
4
Q
5
Q
5
EN
IN
IN
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
V
BB
Q
8
Q
7
V
CCO
Q
7
All V
CC
and V
CCO
pins are tied together on the die
Warning: All V
CC
, V
CCO
, and V
EE
pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. 28−Lead Pinout Assignment
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
PIN
IN, IN
EN
Q0, Q0−Q8, Q8
V
BB
V
CC
, V
CCO
V
EE
NC
FUNCTION
ECL Differential Input Pair
ECL Enable
ECL Differential Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
V
CC
V
CC
R
S
= Z
O
Z
O
RAMBus Load
Z
O
V
OH
and V
OL
levels will vary
slightly from specification table
R
L
= Z
O
V
CC
−2.4
V
300
W
V
EE
Figure 3. Termination Alternatives
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MC10E411
Table 2. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
PLCC−28
PLCC−28
PLCC−28
Condition 1
V
EE
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
8
6
−6
50
100
±
0.5
0 to +85
−65
to +150
63.5
43.5
22 to 26
265
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E411
Table 3. 10E SERIES PECL DC CHARACTERISTICS
V
CCx
= 5.0 V; V
EE
= 0.0 V (Note 1)
0°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
Input HIGH Current
3980
2580
3830
3050
3.62
3.4
Min
Typ
55
4070
2750
3995
3285
Max
65
4160
2920
4160
3520
3.73
4.6
150
4020
2620
3870
3050
3.65
3.4
Min
25°C
Typ
55
4105
2785
4030
3285
Max
65
4190
2950
4190
3520
3.75
4.6
150
4090
2690
3940
3050
3.69
3.4
Min
85°C
Typ
55
4185
2865
4110
3302
Max
65
4280
3040
4280
3555
3.81
4.6
150
Unit
mA
mV
mV
mV
mV
V
V
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.5 V /
−0.5
V.
2. Outputs are terminated through a 300
W
resistor to V
EE
.
3. V
IHCMR
min and max vary 1:1 with V
CC
.
Table 4. 10E SERIES NECL DC CHARACTERISTICS
V
CCx
= 0.0 V; V
EE
=
−5.0
V (Note 4)
0°C
Symbol
I
EE
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Power Supply Current
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
Input HIGH Current
Input LOW Current
0.5
0.3
−1020
−2420
−1170
−1950
−1.38
−1.6
Min
Typ
130
55
−930
−2250
−1005
−1715
Max
156
65
−840
−2080
−840
−1480
−1.27
−2.4
150
0.5
0.065
−980
−2380
−1130
−1950
−1.35
−1.6
Min
25°C
Typ
130
55
−895
−2215
−970
−1715
Max
156
65
−810
−2050
−810
−1480
−1.25
−0.4
150
0.3
0.2
−910
−2310
−1060
−1950
−1.31
−1.6
Min
85°C
Typ
130
55
−815
−2135
−890
−1698
Max
156
65
−720
−1960
−720
−1445
−1.19
−0.4
150
Unit
mA
mA
mV
mV
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.5 V /
−0.5
V.
5. Outputs are terminated through a 300
W
resistor to V
EE
.
6. V
IHCMR
min and max vary 1:1 with V
CC
.
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MC10E411
Table 5. AC CHARACTERISTICS
V
CCx
= 5.0 V; V
EE
= 0.0 V or V
CCx
= 0.0 V; V
EE
=
−5.0
V (Note 7)
0°C
Symbol
f
MAX
t
PLH
t
PHL
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
IN (Differential) (Note 8)
IN (Single−Ended) (Note 9)
EN to Q
Setup Time (Note 10)
Hold Time (Note 11)
Release Time (Note 12)
Within-Device Skew (Note 13)
Part-to-Part Skew (Diff)
Random Clock Jitter (RMS)
Input Voltage Swing
(Differential Configuration)
Output Rise/Fall Time
(20%−80%)
250
275
<1
1000
600
250
275
EN to IN
IN to EN
EN to IN
400
350
450
200
0
300
0
−200
100
50
200
<1
1000
600
250
275
Min
Typ
700
600
650
850
430
380
450
200
0
300
0
−200
100
50
200
<1
1000
600
Max
Min
25°C
Typ
700
630
680
850
500
450
450
200
0
300
0
−200
100
50
200
Max
Min
85°C
Typ
700
700
750
850
Max
Unit
MHz
ps
t
s
t
H
t
R
t
skew
t
JITTER
V
PP
t
r
/t
f
ps
ps
ps
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. V
EE
can vary +0.5 V /
−0.5
V.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75
mV to that IN/IN transition.
11. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response
greater than
±75
mV to that IN/IN transition.
12. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times.
13. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
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