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MC100E445FN

Description
5V ECL 4-Bit Serial/Parallel Converter
Categorylogic    logic   
File Size154KB,13 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Download Datasheet Parametric Compare View All

MC100E445FN Overview

5V ECL 4-Bit Serial/Parallel Converter

MC100E445FN Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerON Semiconductor
Parts packaging codeQLCC
package instructionQCCJ,
Contacts28
Reach Compliance Code_compli
Other featuresNECL MODE: VCC = 0V WITH VEE = -4.2 TO -5.7V
Counting directionRIGHT
series100E
JESD-30 codeS-PQCC-J28
JESD-609 codee0
length11.505 mm
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Number of digits4
Number of functions1
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature
Output characteristicsOPEN-EMITTER
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)240
propagation delay (tpd)2.1 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)5.7 V
Minimum supply voltage (Vsup)4.2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyECL
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn80Pb20)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width11.505 mm
minfmax2000 MHz
MC10E445, MC100E445
5V ECL 4-Bit Serial/Parallel
Converter
Description
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
http://onsemi.com
2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the first serial bit to Q0, the
second to Q1 etc.
PLCC−28
FN SUFFIX
Two selectable serial inputs provide a loopback capability for testing
CASE 776
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
MARKING DIAGRAM*
shifts the start bit for conversion from Qn to Qn−1. For each additional
1 28
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to
“swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn−1
output (see Timing Diagram B).
MCxxxE445FNG
The MODE input is used to select the conversion mode of the device.
AWLYYWW
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the data on the output will
change on every eighth clock cycle thus allowing for an 8-bit conversion
xxx
= 10 or 100
scheme using two E445’s. When cascaded in an 8-bit conversion scheme
A
= Assembly Location
the devices will not operate at the 2.0 Gb/s data rate of a single device.
WL
= Wafer Lot
Refer to the applications section of this data sheet for more information on
YY
= Year
cascading the E445.
WW
= Work Week
Upon power-up the internal flip-flops will attain a random state. To
G
= Pb−Free Package
synchronize multiple E445’s in a system the master reset must be asserted.
The V
BB
pin, an internally generated voltage supply, is available to this
*For additional marking information, refer to
device only. For single-ended input conditions, the unused differential
Application Note AND8002/D.
input is connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
ORDERING INFORMATION
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA. When
See detailed ordering and shipping information in the package
not used, V
BB
should be left open.
dimensions section on page 11 of this data sheet.
The 100 Series contains temperature compensation.
Features
ESD Protection: Human Body Model; > 2 kV,
On-Chip Clock
÷4
and
÷8
Machine Model; > 100 V
2.0 Gb/s Data Rate Capability
Meets or Exceeds JEDEC Spec EIA/JESD78
IC Latchup Test
Differential Clock and Serial Inputs
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
V
BB
Output for Single-Ended Input Applications
For Additional Information, see Application Note
Asynchronous Data Synchronization
AND8003/D
Mode Select to Expand to 8-Bits
Flammability Rating: UL 94 V−0 @ 0.125 in,
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
Oxygen Index: 28 to 34
with V
EE
= 0 V
Transistor Count = 528 devices
NECL Mode Operating Range: V
CC
= 0 V
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
=
−4.2
V to
−5.7
V
with V
EE
= 0 V
Internal Input 50 kW Pulldown Resistors
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
Rev. 12
1
Publication Order Number:
MC10E445/D

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