FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16705-1E
32-bit Proprietary Microcontrollers
CMOS
FR60 MB91319R Series
MB91316/316A/F318R/F318S/FV319R
■
DESCRIPTION
The MB91319R series is the microcontrollers which use a high-performance 32-bit RISC-CPU and contains
various types of I/O resources for the embedded control that requires high-performance and high-speed CPU
processing.
It is suitable for the embedded control in TV or PDP, requiring high-performance CPU processing power.
This product is one of the FR60* family based on the FR30/40 family CPU with enhanced bus access. It is
applicable to faster-speed application.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■
FEATURE
•
FR CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Operating frequency : 40 MHz (Use of PLL : Oscillation 10 MHz)
• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle
• Embedded application optimized instructions : Memory-to-memory transfer, bit processing, barrel shift, and
other instructions.
• High-level language support instructions : Function entry/exit instructions, multiple register load/store
instructions.
• Register interlock functions: Facilitating coding in assemblers
• Built-in multiplier with instruction-level support
32-bit multiplication with sign : 5 cycles
16-bit multiplication with sign : 3 cycles
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB91319R Series
•
•
•
•
Interrupt (PC, PS save) : 6 cycles, 16 priority levels
Harvard architecture allowing program access and data access to be executed simultaneously
Instruction prefetch function implemented by a four-word queue in the CPU
Instruction compatible with FR family
•
Bus interface
This bus interface is used for internal macro IF (USB, OSDC)
• CS1, CS2, and CS3 areas are connected as following :
CS1 area : Reserved, CS2 area : USB function, CS3 area : OSDC
•
Built-in memory
Memory
RAM
Memory for program
Memory for font
MB91FV319R
48 Kbytes
Flash memory : 1 Mbyte
Flash memory : 512 Kbytes
MB91F318R/F318S
48 Kbytes
Flash memory : 1 Mbyte
MASK ROM : 384 Kbytes
MB91316/316A
32 Kbytes
MASK ROM : 512 Kbytes
MASK ROM : 384 Kbytes
•
DMAC (DMA Controller)
• 5 channels (ch.0 and ch.1 are connected to USB function. )
• Two transfer sources (internal peripherals/software)
• Specifying of addressing mode 32-bit full address (increased/decreased/fixed)
• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
• Selectable transfer data size : 8, 16, or 32-bits
•
Bit search module (for REALOS)
• Search for the position of the bit “1”/“0”-changed first in one word from the MSB
•
Reload timer (including a channel for REALOS)
• 16-bit timer: 3 channels
• The internal clock is selectable from 2/8/32 divisions.
•
UART
• Full-duplex double buffer
• 5 channels
• Selectable parity ON/OFF
• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable
• Built-in timer for dedicated baud rate
• External clock can be used as transfer clock.
• Assorted error detection functions (for parity, frame, and overrun errors)
(Continued)
2
MB91319R Series
•
I
2
C Interface *
• 4 channels (built-in bridge function)
• Master/slave sending and receiving
• Clock synchronization function
• Detecting transmitting direction function
• Bus error detection function
• Standard mode (Max 100 kbps) /High speed mode (Max 400 kbps) supported
• Built-in FIFO function with 16-byte data each for transmit/receive
• Arbitration function
• Slave address and general call address detection function
• Start condition repeated generation and detection
• 10-bit/7-bit slave address
•
Interrupt controller
• Total of external interrupt pin is 5. (one non-maskable interrupt pin (NMI) and four normal interrupt pins (INT3
to INT0) )
• Interrupt from internal peripheral
• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
• At the STOP, available use for Wake Up
•
A/D converter
• 10-bit resolution, 10 channels
• Successive approximation type converter. Conversion time: Approx. 10
µs
• Conversion modes (one-shot conversion mode, scanning conversion mode)
• Activation trigger (software / external trigger)
•
PPG
• 4 channels are incorporated.
• 16-bit down counter, 16-bit data register with buffer for setting cycles
• The internal clock is selectable from 1/4/16/64 divisions.
•
PWC
• 1 channel (1 input) is incorporated.
• 16-bit up counter
• Easy digital low pass filter
•
Multi function timer
• 4 channels are incorporated.
• Low pass filter eliminating noise below the clock setting
• Capable of pulse width measurement according to fine settings using seven types of clock signals
• Event count function from pin input
• Interval timer function using seven kinds of clock and external input clock
•
USB function
• Full speed
•
double buffer of USB2.0 version
• CONTROL IN/OUT, BULK IN/OUT, INTERRUPT IN
(Continued)
3
MB91319R Series
(Continued)
•
OSDC function
• RGB: each 3 bits (16 colors available among 512 colors)
• Analog RGB output: Max 50 MHz
• Digital RGB output: Max 90 MHz
• A font in 24
×
32 dots can be displayed up to 80
×
32.
• Two-layered display of MAIN/CC (Font in CC layer is fixed at 18 dots in horizontal axis)
• 4096 characters at the maximum (including 16 characters for font RAM)
•
Closed caption decoder function
• 2 channels are incorporated.
• CC decode function
• ID-1 (480i/480p) decode function
•
PLL for video clock
• 3 PLLs generating dot clock and VBI clock
•
Other interval timer
• 16-bit timer : 3 channels
• Watchdog timer
•
I/O port
• Max 88 ports
•
Other features
• Built-in oscillation circuit as clock source
• INIT is prepared as a reset pin.
• Watchdog timer reset and software reset are also available.
• Stop mode and sleep mode are supported as low-power consumption mode.
• Gear function
• Built-in time-base timer
• Package : LQFP-176, 0.5mm pitch, 24 mm
×
24 mm
• CMOS technology : 0.18
µm
• Power supply voltage : 3.3 V
±
0.3 V, 1.8 V
±
0.15 V 2-power supply
* : “Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these
components in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined
by Philips.”
4
MB91319R Series
■
PIN ASSIGNMENT
(TOP VIEW)
VSYNC
DCKI
DCKO
FH
VOB1
VOB2
VDDI
R2
R1
R0
G2
G1
G0
B2
B1
B0
UDP
UDM
VDDE
X0B
VSS
X1B
VDDI
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
P17
P16/ATRG
P15/PPG3
P14/PPG2
P13/PPG1
P12/PPG0
P11/TMO3
P10/TMO2
P07/TMO1
P06/TMO0
P05/TO2
P04/TO1
P03/TO0
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
HSYNC1
HSYNC2
HSYNC3
VDDE
VSS
VGS1/VCI1
CPO1
VSSP1
VDDP1
VGS2/VCI2
CPO2
VSSP2
VDDP2
VGS3/VCI3
CPO3
VSSP3
VDDP3
VDDR
VREF
VR0
ROUT
VSSR
VDDG
GOUT
VSSG
VDDB
BOUT
VSSB
VIN0
VIN1
VDDIS
VSSS
VDDI
AVCC
AVRH
AVSS/AVRL
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
P94/TMI1
P93/TMI0
P92/RIN
P91/SCK1
P90/SO1
P87/SI1
P86/SCK0
P85/SO0
P84/SI0
P83/SDA1
P82/SCL1
P81/SDA0
P80/SCL0
INIT
MD3
MD2
MD1
MD0
ICD3
ICD2
ICD1
ICD0
ICS2
ICS1
ICS0
IBREAK
ICLK
TRST
VDDI
X1
VSS
X0
VDDE
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21/AN9
P20/AN8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P02/SCK4/TIN2
P01/SO4/TIN1
P00/SI4/TIN0
P74
P73
P72
P71
P70
VDDE
VSS
VDDI
P57
P56
P55
P54
P53
P52/SCK3
P51/SO3
P50/SI3
P47/SCK2
P46/SO2
P45/SI2
P44/SDA4
P43/SDA3
P42/SCL4
P41/SCL3
P40/SDA2
P37/SCL2
P36/TRG3
P35/TRG2
P34/TRG1
P33/TRG0
NMI
PA2/INT3
PA1/INT2
PA0/INT1
VDDI
X1A
VSS
X0A
VDDE
P97/INT0
P96/TMI3
P95/TMI2
(FPT-176P-M07)
5
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