PALCE26V12H-15JI/4 datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> PALCE26V12H-15JI/4

PALCE26V12H-15JI/4: DescriptionEE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28; CategoryProgrammable logic devices Programmable logic; File Size211KB，21 Pages; ManufacturerAMD; Websitehttp://www.amd.com

Download Datasheet Parametric Compare View All

PALCE26V12H-15JI/4 Overview

EE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28

PALCE26V12H-15JI/4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QLCC
package instruction	QCCJ, LDCC28,.5SQ
Contacts	28
Reach Compliance Code	unknown
Other features	12 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 2 EXTERNAL CLOCKS
Architecture	PAL-TYPE
maximum clock frequency	50 MHz
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.5062 mm
Dedicated input times	12
Number of I/O lines	12
Number of entries	26
Output times	12
Number of product terms	136
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	12 DEDICATED INPUTS, 12 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.5062 mm
Base Number Matches	1

Preview

Download Datasheet

View All

FINAL

COM’L: H-7/10/15/20

IND: H-10/15/20

PALCE26V12 Family

28-Pin EE CMOS Versatile PAL Device

DISTINCTIVE CHARACTERISTICS

28-pin versatile PAL programmable logic

device architecture

Electrically erasable CMOS technology

provides half power (only 115 mA) at high

speed (7.5 ns propagation delay)

14 dedicated inputs and 12 input/output

macrocells for architectural flexibility

Macrocells can be registered or combinatorial,

and active high or active low

Varied product term distribution allows up to

16 product terms per output

Two clock inputs for independent functions

Global asynchronous reset and synchronous

preset for initialization

Space-efficient 28-pin SKINNYDIP and PLCC

packages

Center VCC and GND pins to improve signal

characteristics

Extensive third-party software and programmer

support through FusionPLD partners

GENERAL DESCRIPTION

The PALCE26V12 is a 28-pin version of the popular

PAL22V10 architecture. Built with low-power, high-

speed, electrically-erasable CMOS technology, the

PALCE26V12 offers many unique advantages.

Device logic is automatically configured according to

the user’s design specification. Design is simplified by

design software, allowing automatic creation of a

programming file based on Boolean or state equations.

The software can also be used to verify the design and

can provide test vectors for the programmed device.

The PALCE26V12 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced

to sum-of-products form, taking advantage of the

very wide input gates available in PAL devices. The

functions are programmed into the device through

electrically-erasable floating-gate cells in the AND logic

array and the macrocells. In the unprogrammed state,

all AND product terms float HIGH. If both true and

complement of any input are connected, the term will be

permanently LOW.

The product terms are connected to the fixed OR array

with a varied distribution from 8 to 16 across the outputs

(see Block Diagram). The OR sum of the products feeds

the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial, active high or

active low, with registered I/O possible. The flip-flop can

be clocked by one of two clock inputs. The output

configuration is determined by four bits controlling three

multiplexers in each macrocell.

AMD’s FusionPLD program allows PALCE26V12

designs to be implemented using a wide variety of

popular industry-standard design tools. By working

closely with the FusionPLD partners, AMD certifies that

the tools provide accurate, quality support. By ensuring

that third-party tools are available, costs are lowered

because a designer does not have to buy a complete set

of new tools for each device. The FusionPLD program

also greatly reduces design time since a designer can

use a tool that is already installed and familiar. Please

refer to the PLD Software Reference Guide for certified

development systems and the Programmer Reference

Guide for approved programmers.

2-306

Publication#

16072

Rev.

Issue Date:

February 1996

Amendment

PALCE26V12H-15JI/4 Related Products

	PALCE26V12H-15JI/4	PALCE26V12H-7PC	PALCE26V12H-10PC/4	PALCE26V12H-10PI/4	PALCE26V12H-15PI/4	PALCE26V12H-20JI/4	PALCE26V12H-7JC/4
Description	EE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28	28-pin EE cmos versatile pal device	EE PLD, 10ns, PAL-Type, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28	EE PLD, 10ns, PAL-Type, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28	EE PLD, 15ns, PAL-Type, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28	EE PLD, 20ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28	EE PLD, 8ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
Is it Rohs certified?	incompatible	-	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	QLCC	-	DIP	DIP	DIP	QLCC	QLCC
package instruction	QCCJ, LDCC28,.5SQ	-	DIP, DIP28,.3	DIP, DIP28,.3	DIP, DIP28,.3	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ
Contacts	28	-	28	28	28	28	28
Reach Compliance Code	unknown	-	unknown	unknown	unknown	unknown	unknown
Other features	12 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 2 EXTERNAL CLOCKS	-	12 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 2 EXTERNAL CLOCKS	12 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 2 EXTERNAL CLOCKS	12 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 2 EXTERNAL CLOCKS	12 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 2 EXTERNAL CLOCKS	12 MACROCELLS; REGISTER PRELOAD; SHARED INPUT/CLOCK; 2 EXTERNAL CLOCKS
Architecture	PAL-TYPE	-	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE
maximum clock frequency	50 MHz	-	71.4 MHz	71.4 MHz	50 MHz	40 MHz	105.3 MHz
JESD-30 code	S-PQCC-J28	-	R-PDIP-T28	R-PDIP-T28	R-PDIP-T28	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e0	-	e0	e0	e0	e0	e0
length	11.5062 mm	-	35.2425 mm	35.2425 mm	35.2425 mm	11.5062 mm	11.5062 mm
Dedicated input times	12	-	12	12	12	12	12
Number of I/O lines	12	-	12	12	12	12	12
Number of entries	26	-	26	26	26	26	26
Output times	12	-	12	12	12	12	12
Number of product terms	136	-	136	136	136	136	136
Number of terminals	28	-	28	28	28	28	28
Maximum operating temperature	85 °C	-	75 °C	85 °C	85 °C	85 °C	75 °C
Minimum operating temperature	-40 °C	-	-	-40 °C	-40 °C	-40 °C	-
organize	12 DEDICATED INPUTS, 12 I/O	-	12 DEDICATED INPUTS, 12 I/O	12 DEDICATED INPUTS, 12 I/O	12 DEDICATED INPUTS, 12 I/O	12 DEDICATED INPUTS, 12 I/O	12 DEDICATED INPUTS, 12 I/O
Output function	MACROCELL	-	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	-	DIP	DIP	DIP	QCCJ	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ	-	DIP28,.3	DIP28,.3	DIP28,.3	LDCC28,.5SQ	LDCC28,.5SQ
Package shape	SQUARE	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE
Package form	CHIP CARRIER	-	IN-LINE	IN-LINE	IN-LINE	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	-	5 V	5 V	5 V	5 V	5 V
Programmable logic type	EE PLD	-	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	15 ns	-	10 ns	10 ns	15 ns	20 ns	8 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	-	5.08 mm	5.08 mm	5.08 mm	4.572 mm	4.572 mm
Maximum supply voltage	5.5 V	-	5.25 V	5.5 V	5.5 V	5.5 V	5.25 V
Minimum supply voltage	4.5 V	-	4.75 V	4.5 V	4.5 V	4.5 V	4.75 V
Nominal supply voltage	5 V	-	5 V	5 V	5 V	5 V	5 V
surface mount	YES	-	NO	NO	NO	YES	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	-	COMMERCIAL EXTENDED	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	-	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	J BEND	J BEND
Terminal pitch	1.27 mm	-	2.54 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm
Terminal location	QUAD	-	DUAL	DUAL	DUAL	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	11.5062 mm	-	7.62 mm	7.62 mm	7.62 mm	11.5062 mm	11.5062 mm
Base Number Matches	1	-	1	1	1	1	1

Recommended Resources

One of the regulated power supply overload indication circuits

Monostable multivibrator circuit with input blocking

5MHz phase encoded data readout circuit

Camera power and video common coaxial cable circuit

TP-10A type 25W outdoor rainproof FM speaker circuit diagram

ADI Prize Download Event 15: ADI's Smart Wearable Healthcare Device Solutions: [font=微软雅黑][size=4]Event details: [url=https://www.eeworld.com.cn/huodong/ADI-15/index.php]https://www.eeworld.com.cn/huodong/ADI-15/index.php[/url] [/size][/font] [font=微软雅黑][size=4]Event date: Now -...; EEWORLD社区 ADI Reference Circuit

LPC1500 experience + BLDC/PMSM motor drive [prelude post] Fairchild FNB41060 SPM module design reference material sharing: The LPC1500 series MCU is very suitable for BLDC motor drive control, especially in sensorless applications. The built-in analog comparator and high-speed ADC can be easily used in the back-EMF detect...; foxpro2005 NXP MCU

I embedded a uclinux kernel in the soc, and an error occurred when compiling the kernel. I hope the experts can help me solve it.: [img]file:///C:/Users/Administrator/Documents/Tencent%20Files/351902767/Image/Group/V0Y3N2ESG2WDIZX2B)9%25OU5.png[/img]Hello everyone, I would like to ask you a question. When I executed make menuconf...; xusiyan0217 FPGA/CPLD

Why can't waveform be generated by automatically generating simulation through quartus?: After writing the .v file and the .vt file, I directly called modelsim through quartu[img=0,1]file:///C:\Users\lx\AppData\Roaming\Tencent\Users\870481988\QQ\WinTemp\RichOle\QCI)4{VFCWL]]S058Z8V]{R.png...; 我爱麦迪 FPGA/CPLD

A feast for the eyes! MSP430 at Maker Faire NC 2013: [b][size=5]Maker Faire NC 2013 is an exhibition held by makezine magazine every year in [color=#262626]North Carolina[/color][/size][/b][size=5]. It was just held yesterday. Let’s take a look at the M...; wstt Microcontroller MCU

Where do we need monitoring systems?: a. Service industries such as hotels, banks, restaurants, and entertainment venues. Competition in the service industry is becoming increasingly fierce, and people have higher requirements for the ser...; jek9528 Industrial Control Electronics

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components