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70T9159L12BF

Description
CABGA-100, Tray
Categorystorage    storage   
File Size549KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

70T9159L12BF Overview

CABGA-100, Tray

70T9159L12BF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeCABGA
package instructionBGA, BGA100,10X10,32
Contacts100
Manufacturer packaging codeBF100
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time12 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)50 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B100
JESD-609 codee0
length10 mm
memory density147456 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count16384 words
character code16000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16KX9
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA100,10X10,32
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5 V
Certification statusNot Qualified
Maximum seat height1.5 mm
Maximum standby current0.003 A
Minimum standby current2.4 V
Maximum slew rate0.15 mA
Maximum supply voltage (Vsup)2.6 V
Minimum supply voltage (Vsup)2.4 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width10 mm
Base Number Matches1
HIGH-SPEED 2.5V
16/8K X 9 SYNCHRONOUS
PIPELINED
DUAL-PORT STATIC RAM
Features
IDT70T9169/59L
OBSOLETE PARTS
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:7.5/9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70T9169/59L
Active: 225mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
FT/PIPE
L
I/O
0L
- I/O
8L
S OR
T F
R
A D
P E
E ND S
T E
E
N
L M IG
O M S
S O
E
B C
D
O E
R EW
T N
O
N
1
0
0/1
1
0
0/1
0/1
1
0
0
1
0/1
Full synchronous operation on both ports
– 4.0ns setup to clock and 0.5ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
LVTTL- compatible, single 2.5V (±100mV) power supply
Industrial temperature range (–40°C to +85°C) is
available for 66MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages
R/W
R
OE
R
CE
0R
CE
1R
FT/PIPE
R
I/O
0R
- I/O
8R
I/O
Control
I/O
Control
A
13L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
13R
(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
5654 drw 01
NOTE:
1. A
13
is a NC for IDT70T9159.
JANUARY 2009
1
©2009 Integrated Device Technology, Inc.
DSC-5654/3
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