January 2008
HYS64T32[0/9]00EU-[25F/2.5/3/3S/3.7]-B2
HYS[64/72]T64[0/9]00EU-[25F/2.5/3/3S/3.7]-B2
HYS[64/72]T128[0/9]20EU-[25F/2.5/3/3S/3.7]-B2
240-Pin Unbuffered DDR2 SDRAM Modules
UDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.01
Internet Data Sheet
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
Unbuffered DDR2 SDRAM Module
HYS64T32[0/9]00EU-[25F/2.5/3/3S/3.7]-B2, HYS[64/72]T64[0/9]00EU-[25F/2.5/3/3S/3.7]-B2, HYS[64/72]T128[0/9]20EU-
[25F/2.5/3/3S/3.7]-B2
Revision History: 2008-01, Rev. 1.01
Page
All
All
4,5
16 – 20
34,35
38 – 42
45 – 92
Subjects (major changes since last revision)
Editorial change and adapted to internet edition
Qimonda update
Ordering information table. Added 6LayerWhiteBox Products.
Block Diagrams: Clock Signal Load Tables and Notes updated
ODT table update
Added IDD values.
SPD codes updated.
Previous Revision: 2006-10, Rev. 1.0
Previous Revision: 2006-07, Rev. 0.5
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
10202006-L0SM-FEYT
2
Internet Data Sheet
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
Unbuffered DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-pin Unbuffered DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh.
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
µs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
Serial Presence Detect with E
2
PROM
UDIMM and EDIMM Dimensions (nominal): 30 mm high,
133.35 mm wide.
Based on standard reference layouts Raw Cards 'C', 'D',
'E', ’F' and 'G'
RoHS compliant products
1)
• 240-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2
SDRAM memory modules.
• Two ranks 128M
×
64, 128M
×
72, and one rank 32M
×
64,
64M
×
64, 64M
×
72 module organization, and 32M
×
16,
64M
×
8 chip organization
• 1GB, 512MB, 256MB Modules built with 512Mbit DDR2
SDRAMs in P-TFBGA-60 and PG-TFBGA-84 chipsize
packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
Length (8 & 4).
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max.
Clock Frequency
CL3
CL4
CL5
CL6
DDR2
PC2
–25F
–800D
–6400D
5–5–5
–2.5
–800E
–6400E
6–6–6
200
266
333
–3
–667C
–5300C
4–4–4
200
333
333
–3S
–667D
–5300D
5–5–5
200
266
333
–
15
15
45
60
–3.7
–533C
–4200C
4–4–4
200
266
266
–
15
15
45
60
Unit
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
ns
–
400
–
Min. RAS-CAS-Delay
12.5
15
12
Min. Row Precharge Time
12.5
15
12
1)
Min. Row Active Time
45
45
45
Min. Row Cycle Time
57.5
60
57
1) Product released after 01-08-2007 will support
t
RAS
= 40 ns for all DDR2 speed sort.
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
t
RC
200
266
400
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.01, 2008-01
10202006-L0SM-FEYT
3
Internet Data Sheet
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
Unbuffered DDR2 SDRAM Module
1.2
Description
The memory array is designed with 512Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The
Qimonda
HYS[64/72]T[32/64/128]xxxEU-
[25F/2.5/3/3S/3.7]-B2 module family are Unbuffered DIMM
modules “UDIMMs” with 30 mm height based on DDR2
technology.
DIMMs are available as non-ECC modules
in
128M
×
72 (1GB), 32M
×
64 (256MB), 64M
×
64 (512MB)
and
as
ECC
modules
in
128M
×
72 (1GB),
64M
×
72 (512MB) in organization and density, intended for
mounting into 240-pin connector sockets.
TABLE 2
Ordering Information
Product Type
1)
PC2-6400 (5-5-5)
HYS72T128920EU–25F–B2
HYS64T128920EU–25F–B2
HYS72T128020EU–25F–B2
HYS64T128020EU–25F–B2
HYS72T64900EU–25F–B2
HYS64T64900EU–25F–B2
HYS72T64000EU–25F–B2
HYS64T64000EU–25F–B2
HYS64T32900EU–25F–B2
HYS64T32000EU–25F–B2
PC2-6400 (6-6-6)
HYS72T128920EU–2.5–B2
HYS64T128920EU–2.5–B2
HYS72T128020EU–2.5–B2
HYS64T128020EU–2.5–B2
HYS72T64900EU–2.5–B2
HYS64T64900EU–2.5–B2
HYS72T64000EU–2.5–B2
HYS64T64000EU–2.5–B2
HYS64T32900EU–2.5–B2
HYS64T32000EU–2.5–B2
PC2-5300 (4-4-4)
HYS72T128920EU–3–B2
HYS64T128920EU–3–B2
HYS72T128020EU–3–B2
1GB 2R×8 PC2–5300E–444–12–G0
1GB 2R×8 PC2–5300U–444–12–E0
1GB 2R×8 PC2–5300E–444–12–G0
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
1GB 2R×8 PC2–6400E–666–12–G0
1GB 2R×8 PC2–6400U–666–12–E0
1GB 2R×8 PC2–6400E–666–12–G0
1GB 2R×8 PC2–6400U–666–12–E0
512MB 1R×8 PC2–6400E–666–12–F0
512MB 1R×8 PC2–6400U–666–12–D0
512MB 1R×8 PC2–6400E–666–12–F0
512MB 1R×8 PC2–6400U–666–12–D0
256MB 1R×16 PC2–6400U–666–12–C1
256MB 1R×16 PC2–6400U–666–12–C1
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
1GB 2R×8 PC2–6400E–555–12–G0
1GB 2R×8 PC2–6400U–555–12–E0
1GB 2R×8 PC2–6400E–555–12–G0
1GB 2R×8 PC2–6400U–555–12–E0
512MB 1R×8 PC2–6400E–555–12–F0
512MB 1R×8 PC2–6400U–555–12–D0
512MB 1R×8 PC2–6400E–555–12–F0
512MB 1R×8 PC2–6400U–555–12–D0
256MB 1R×16 PC2–6400U–555–12–C1
256MB 1R×16 PC2–6400U–555–12–C1
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
Compliance Code
2)
Description
SDRAM Technology
Rev. 1.01, 2008-01
10202006-L0SM-FEYT
4
Internet Data Sheet
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
Unbuffered DDR2 SDRAM Module
Product Type
1)
HYS64T128020EU–3–B2
HYS72T64900EU–3–B2
HYS64T64900EU–3–B2
HYS72T64000EU–3–B2
HYS64T64000EU–3–B2
HYS64T32900EU–3–B2
HYS64T32000EU–3–B2
PC2-5300 (5-5-5)
HYS72T128920EU–3S–B2
HYS64T128920EU–3S–B2
HYS72T128020EU–3S–B2
HYS64T128020EU–3S–B2
HYS72T64900EU–3S–B2
HYS64T64900EU–3S–B2
HYS72T64000EU–3S–B2
HYS64T64000EU–3S–B2
HYS64T32900EU–3S–B2
HYS64T32000EU–3S–B2
PC2-4200 (4-4-4)
HYS72T128920EU–3.7–B2
HYS64T128920EU–3.7–B2
HYS72T128020EU–3.7–B2
HYS64T128020EU–3.7–B2
HYS72T64900EU–3.7–B2
HYS64T64900EU–3.7–B2
HYS72T64000EU–3.7–B2
HYS64T64000EU–3.7–B2
HYS64T32900EU–3.7–B2
HYS64T32000EU–3.7–B2
Compliance Code
2)
1GB 2R×8 PC2–5300U–444–12–E0
512MB 1R×8 PC2–5300E–444–12–F0
512MB 1R×8 PC2–5300U–444–12–D0
512MB 1R×8 PC2–5300E–444–12–F0
512MB 1R×8 PC2–5300U–444–12–D0
256MB 1R×16 PC2–5300U–444–12–C1
256MB 1R×16 PC2–5300U–444–12–C1
1GB 2R×8 PC2–5300E–555–12–G0
1GB 2R×8 PC2–5300U–555–12–E0
1GB 2R×8 PC2–5300E–555–12–G0
1GB 2R×8 PC2–5300U–555–12–E0
512MB 1R×8 PC2–5300E–555–12–F0
512MB 1R×8 PC2–5300U–555–12–D0
512MB 1R×8 PC2–5300E–555–12–F0
512MB 1R×8 PC2–5300U–555–12–D0
256MB 1R×16 PC2–5300U–555–12–C1
256MB 1R×16 PC2–5300U–555–12–C1
1GB 2R×8 PC2–4200E–444–12–G0
1GB 2R×8 PC2–4200U–444–12–E0
1GB 2R×8 PC2–4200E–444–12–G0
1GB 2R×8 PC2–4200U–444–12–E0
512MB 1R×8 PC2–4200E–444–12–F0
512MB 1R×8 PC2–4200U–444–12–D0
512MB 1R×8 PC2–4200E–444–12–F0
512MB 1R×8 PC2–4200U–444–12–D0
256MB 1R×16 PC2–4200U–444–12–C1
256MB 1R×16 PC2–4200U–444–12–C1
Description
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
SDRAM Technology
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400E–555–12–G0" where 6400E
means Unbuffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency =5,
Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced on
the Raw Card "G".
TABLE 3
Address Format
DIMM
Density
1GB
1GB
Module
Organization
128M
×
72
128M
×
64
Memory
Ranks
2
2
ECC/
Non-ECC
ECC
Non-ECC
# of SDRAMs # of row/bank/column
bits
18
16
14/2/10
14/2/10
Raw
Card
G
E
Rev. 1.01, 2008-01
10202006-L0SM-FEYT
5
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