64Mb Synchronous DRAM based on 512K x 4Bank x32 I/O
Document Title
4Bank x 512K x 32bits Synchronous DRAM
Revision History
Revision No.
0.1
0.2
0.3
History
1) Initial Version Release
1) Corrected OREDERING INFORMATION
1) Corrected a type error at BALL CONFIGURATION
Draft Date
Jan. 2005
Jan. 2005
Feb. 2005
Remark
Preliminary
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.3 / Feb. 2005
1
1
11
Preliminary
Synchronous DRAM Memory 64Mbit (2Mx32bit)
HY5V62D(L/S)F(P) Series
DESCRIPTION
The Hynix HY5V62D(L/S)F(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory appli-
cations which require wide data I/O and high bandwidth. HY5V62D(L/S)F(P) is organized as 4banks of 524,228 x 32.
HY5V62D(L/S)F(P) series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
•
•
Voltage : VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM 0, 1, 2 and DQM 3
•
Internal four banks operation
•
Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
•
•
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Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part Number
HY5V62DF(P)
1
-55
HY5V62DF(P)
1
-6
HY5V62DF(P)
1
-7
HY5V62DLF(P)
1
-55
HY5V62DLF(P)
1
-6
Clock
Frequency
183MHz
166MHz
143MHz
183MHz
166MHz
143MHz
183MHz
166MHz
143MHz
Power
Organization
Interface
Package
Normal
Low
Power
4Banks x 512Kbits x32
LVTTL
90 Ball FBGA
HY5V62DLF(P)
1
-7
HY5V62DSF(P)
1
-55
HY5V62DSF(P)
1
-6
Super Low
Power
HY5V62DSF(P)
1
-7
Note:
1. P: 90Ball FBGA Lead Free Package.
Rev. 0.3 / Feb. 2005
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1
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Preliminary
Synchronous DRAM Memory 64Mbit (2Mx32bit)
HY5V62D(L/S)F(P) Series
BALL DESCRIPTIONS
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A10
RAS, CAS, WE
DQM0 ~
DQM3
DQ0 ~ DQ31
VDD / VSS
VDDQ / VSSQ
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock: The system clock input. All other inputs are registered to the SDRAM on the rising
edge of CLK
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among (deep) power down, suspend or self refresh
Chip Select: Enables or disables all inputs except CLK, CKE and DQM
Bank Address: Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA10, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask: Controls output buffers in read mode and masks input data in write mode
Data Input / Output: Multiplexed data input / output pin
Power supply
I/O Power supply
No connection : These pads should be left unconnected
Rev. 0.3 / Feb. 2005
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